AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 584

• Manufacturer Part Number: AT32UC3A0128-ALUT
• Description: IC MCU AVR32 128KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AT32UC3A
Clear by software (by setting the FIFOCONC bit) to free the current bank and to switch to the next bank.
• EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable
Set by software (by setting the EPDISHDMAS bit) to pause the on-going DMA channel X transfer on any Endpoint X inter-
rupt (EPXINT), whatever the state of the Endpoint X Interrupt Enable bit (EPXINTE).
The software then has to acknowledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (by
setting the EPDISHDMAC bit) in order to complete the DMA transfer.
In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is
running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet
DMA transfer will not start (not requested).
If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may
occur at any time and may immediately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to com-
plete a DMA transfer by software after reception of a short packet, etc.
• RSTDT: Reset Data Toggle
Set by software (by setting the RSTDTS bit) to clear the data toggle sequence, i.e. to set to Data0 the data toggle sequence
of the next sent (IN endpoints) or received (OUT endpoints) packet.
Cleared by hardware instantaneously.
The software does not have to wait for this bit to be cleared.
• STALLRQ: STALL Request
Set by software (by setting the STALLRQS bit) to request to send a STALL handshake to the host.
Cleared by hardware when a new SETUP packet is received.
Can also be cleared by software by setting the STALLRQC bit.
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