AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 625

• Manufacturer Part Number: AT32UC3A0128-ALUT
• Description: IC MCU AVR32 128KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

• OVERFIE: Overflow Interrupt Enable
Set by software (by setting the OVERFIES bit) to enable the Overflow interrupt (OVERFIE).
Clear by software (by setting the OVERFIEC bit) to disable the Overflow interrupt (OVERFIE).
• RXSTALLDE: Received STALLed Interrupt Enable
Set by software (by setting the RXSTALLDES bit) to enable the Received STALLed interrupt (RXSTALLDE).
Clear by software (by setting the RXSTALLDEC bit) to disable the Received STALLed interrupt (RXSTALLDE).
• CRCERRE: CRC Error Interrupt Enable
Set by software (by setting the CRCERRES bit) to enable the CRC Error interrupt (CRCERRE).
Clear by software (by setting the CRCERREC bit) to disable the CRC Error interrupt (CRCERRE).
• SHORTPACKETIE: Short Packet Interrupt Enable
Set by software (by setting the SHORTPACKETES bit) to enable the Short Packet interrupt (SHORTPACKETIE).
Clear by software (by setting the SHORTPACKETEC bit) to disable the Short Packet interrupt (SHORTPACKETE).
• NBUSYBKE: Number of Busy Banks Interrupt Enable
Set by software (by setting the NBUSYBKES bit) to enable the Number of Busy Banks interrupt (NBUSYBKE).
Clear by software (by setting the NBUSYBKEC bit) to disable the Number of Busy Banks interrupt (NBUSYBKE).
• FIFOCON: FIFO Control
For OUT and SETUP Pipe :
Set by hardware when the current bank is free, at the same time than TXOUTI or TXSTPI.
Clear by software (by setting the FIFOCONC bit) to send the FIFO data and to switch the bank.
For IN Pipe:
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
See EPDISHDMA (UECONX register).
• PFREEZE: Pipe Freeze
Set by software (by setting the PFREEZES bit) to Freeze the Pipe requests generation.
Clear by software (by setting the PFREEZEC bit) to enable the Pipe request generation.
This bit is set by hardware when:
- the pipe is not configured
- a STALL handshake has been received on this Pipe
- An error occurs on the Pipe (PERR = 1)
- (INRQ+1) In requests have been processed
This bit is set at 1 by hardware after a Pipe reset or a Pipe enable.
• RSTDT: Reset Data Toggle
Set by software (by setting the RSTDTS bit) to reset the Data Toggle to its initial value for the current Pipe.
Cleared by hardware when proceed.
32058J–AVR32–04/11
Set by hardware when a new IN message is stored in the current bank, at the same time than RXINI.
Clear by software (by setting the FIFOCONC bit) to free the current bank and to switch to the next bank.
AT32UC3A
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