AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 736

• Manufacturer Part Number: AT32UC3A0128-ALUT
• Description: IC MCU AVR32 128KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

35.4.1.1
35.4.1.2
32058J–AVR32–04/11
Debug Communication Channel
Breakpoints
Figure 35-2. JTAG-based debugger
The Debug Communication Channel (DCC) consists of a pair OCD registers with associated
handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange
data between the CPU and the JTAG master, both runtime as well as in debug mode.
One of the most fundamental debug features is the ability to halt the CPU, to examine registers
and the state of the system. This is accomplished by breakpoints, of which many types are
available:
When a breakpoint triggers, the CPU enters debug mode, and the D bit in the status register is
set. This is a privileged mode with dedicated return address and return status registers. All privi-
leged instructions are permitted. Debug mode can be entered as either OCD Mode, running
instructions from JTAG, or Monitor Mode, running instructions from program memory.
• Unconditional breakpoints are set by writing OCD registers by JTAG, halting the CPU
• Program breakpoints halt the CPU when a specific address in the program is executed.
• Data breakpoints halt the CPU when a specific memory address is read or written, allowing
• Software breakpoints halt the CPU when the breakpoint instruction is executed.
immediately.
variables to be watched.
JTAG-based
debug tool
10-pin IDC
AVR32
JTAG
PC
AT32UC3A
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