AT89C5132-ROTUL Atmel, AT89C5132-ROTUL Datasheet - Page 149
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AT89C5132-ROTUL
Manufacturer Part Number
AT89C5132-ROTUL
Description
IC 8051 MCU FLASH 64K USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5132-ROTUL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Cpu Family
89C
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
IDE/SPI/UART/USB
Total Internal Ram Size
2.25KB
# I/os (max)
44
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
On-chip Adc
2-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
TQFP
Package
80TQFP
Family Name
89C
Maximum Speed
40 MHz
Operating Supply Voltage
3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
44
Number Of Timers
2
Maximum Clock Frequency
20 MHz
Data Ram Size
2304 B
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
2
Height
1.45 mm
Length
14.1 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.7 V
Width
14.1 mm
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
21.1.4
21.1.5
21.1.6
4173E–USB–09/07
Configuration
Conversion Launching
End Of Conversion
version (see Section "End Of Conversion", page 149). This bit is cleared by hardware at the end
of the conversion.
Notes:
The ADC configuration consists in programming the ADC clock as detailed in the Section "Clock
Generator", page 148. The ADC is enabled using the ADEN bit in ADCON register. As shown in
Figure 93, user must wait the setup time (T
Figure 21-4. ADC Configuration Flow
The conversion is launched by setting the ADSST bit in ADCON register, this bit remains set
during the conversion. As soon as the conversion is started, it takes 11 clock periods (T
before the data is available in ADDH and ADDL registers.
Figure 21-5. ADC Conversion Launching Flow
The end of conversion is signalled by the ADEOC flag in ADCON register becoming set or by the
ADSST bit in ADCON register becoming cleared. ADEOC flag can generate an interrupt if
1. Only the CPU activity is frozen, peripherals are not affected by the Pseudo-Idle mode.
2. If some interrupts occur during the Pseudo-Idle mode, they will be delayed and processed,
3. Concurrently with ADSST bit.
according to their priority after the end of the conversion.
Program ADC Clock
Conversion Start
ADCD4:0 = xxxxxb
Start Conversion
Wait Setup Time
Configuration
Select Channel
Enable ADC
SETUP
ADCS = 0-1
ADSST = 1
ADIDL = x
ADEN = 1
ADC
ADC
) before launching any conversion.
AT89C5132
CONV
149
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