AT32UC3A0256-ALUT Atmel, AT32UC3A0256-ALUT Datasheet - Page 118

• Manufacturer Part Number: AT32UC3A0256-ALUT
• Description: IC MCU AVR32 256KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0256-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 144LQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.4.7
18.5
32058J–AVR32–04/11
Flash commands
Writing words to a page that is not completely erased
The page buffer is also used for writes to the User page.
Write operations can be prevented by programming the Memory Protection Unit of the CPU.
Writing 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable
data corruption.
Page buffer write operations are performed with 4 wait states.
Writing to the page buffer can only change page buffer bits from one to zero, ie writing
0xaaaaaaaa to a page buffer location that has the value 0x00000000, will not change the page
buffer value. The only way to change a bit from zero to one, is to reset the entire page buffer
with the Clear Page Buffer command.
The page buffer is not automatically reset after a page write. The programmer should do this
manually by issuing the Clear Page Buffer flash command. This can be done after a page
write, or before the page buffer is loaded with data to be stored to the flash page.
Example: Writing a word into word address 130 of a flash with 128 words in the page buffer.
PAGEN will be updated with the value 1, and the word will be written into word 2 in the page
buffer.
This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an
entire page. Only words that are in an completely erased state (0xFFFFFFFF) can be
changed. The procedure is as follows:
The FLASHC offers a command set to manage programming of the flash memory, locking and
unlocking of regions, and full flash erasing. See chapter 18.8.3 for a complete list of
commands.
To run a command, the field CMD of the Flash Command Register (FCMD) has to be written
with the command number. As soon as the FCMD register is written, the FRDY flag is auto-
matically cleared. Once the current command is complete, the FRDY flag is automatically set.
If an interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash
controller is activated. All flash commands except for Quick Page Read (QPR) will generate an
interrupt request upon completion if FRDY is set.
After a command has been written to FCMD, the programming algorithm should wait until the
command has been executed before attempting to read instructions or data from the flash or
writing to the page buffer, as the flash will be busy. The waiting can be performed either by
polling the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The com-
mand written to FCMD is initiated on the first clock cycle where the HSB bus interface in
FLASHC is IDLE. The user must make sure that the access pattern to the FLASHC HSB inter-
face contains an IDLE cycle so that the command is allowed to start. Make sure that no bus
masters such as DMA controllers are performing endless burst transfers from the flash. Also,
make sure that the CPU does not perform endless burst transfers from flash. This is done by
1. Clear page buffer
2. Write to the page buffer the result of the logical bitwise AND operation between the
3. Write Page.
contents of the flash page and the new data to write. Only words that were in an
erased state can be changed from the original page.
AT32UC3A
118