AT32UC3A0256-ALUT Atmel, AT32UC3A0256-ALUT Datasheet - Page 514

• Manufacturer Part Number: AT32UC3A0256-ALUT
• Description: IC MCU AVR32 256KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0256-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 64KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 144LQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

30.7.2.10
30.7.2.10.1 Special Considerations for Control Endpoints
30.7.2.10.2 STALL Handshake and Retry Mechanism
30.7.2.11
30.7.2.11.1 Overview
32058J–AVR32–04/11
STALL Request
Management of Control Endpoints
• The firmware may then set the RMWKUP bit to send an upstream resume to the host for a
• When the controller sends the upstream resume, the Upstream Resume interrupt (UPRSM) is
• RMWKUP is cleared by hardware at the end of the upstream resume.
• If the controller detects a valid “End of Resume” signal from the host, the End of Resume
For each endpoint, the STALL management is performed using:
To answer the next request with a STALL handshake, STALLRQ has to be set by setting the
STALLRQS bit. All following requests will be discarded (RXOUTI, etc. will not be set) and hand-
shaked with a STALL until the STALLRQ bit is cleared, what is done by hardware when a new
SETUP packet is received (for control endpoints) or when the STALLRQC bit is set.
Each time a STALL handshake is sent, the STALLEDI flag is set by the USB controller and the
EPXINT interrupt is raised.
If a SETUP packet is received into a control endpoint for which a STALL is requested, the
Received SETUP interrupt (RXSTPI) is raised and STALLRQ and STALLEDI are cleared by
hardware. The SETUP has to be ACKed.
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the firmware requests a STALL and can return to the main task,
waiting for the next SETUP request.
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ bit is set and if there is no retry required.
A SETUP request is always ACKed. When a new SETUP packet is received, the Received
SETUP interrupt (RXSTPI) is raised, but not the Received OUT Data interrupt (RXOUTI).
The FIFOCON and RWALL bits are irrelevant for control endpoints. The firmware shall therefore
never use them on these endpoints. When read, their value is always 0.
Control endpoints are managed using:
remote wake-up. This will automatically be done by the controller after 5 ms of inactivity on the
USB bus.
raised and SUSP is cleared by hardware.
interrupt (EORSM) is raised.
•the STALL Request bit (STALLRQ) to initiate a STALL request;
•the STALLed interrupt (STALLEDI) raised when a STALL handshake has been sent.
•the Received SETUP interrupt (RXSTPI) which is raised when a new SETUP packet is
received and which shall be cleared by firmware to acknowledge the packet and to free the
bank;
AT32UC3A
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