P87C52SBPN,112 NXP Semiconductors, P87C52SBPN,112 Datasheet - Page 23

• Manufacturer Part Number: P87C52SBPN,112
• Description: IC 80C51 MCU 8K OTP 40-DIP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C52SBPN,112

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1012-5; 935253690112; P87C52SBPN

Philips Semiconductors
DC ELECTRICAL CHARACTERISTICS
T
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
3. Capacitive loading on ports 0 and 2 may cause the V
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
5. See Figures 22 through 25 for I
6. This value applies to T
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I
9. ALE is tested to V
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection
2000 Aug 07
amb
SYMBOL
SYMBOL
V
V
V
V
V
V
V
I
I
I
I
R
C
IL
TL
LI
CC
IL
IH
IH1
OL
OL1
OH
OH1
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
RST
IO
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
address bits are stabilizing.
maximum value when V
If I
test conditions.
(except EA is 25 pF).
circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
= 0 C to +70 C or –40 C to +85 C, 33 MHz devices; 5 V 10%; V
OL
Active mode:
Idle mode:
Maximum I
Maximum I
Maximum total I
exceeds the test condition, V
Input low voltage
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, 3
Output low voltage, port 0, ALE, PSEN
Output high voltage, ports 1, 2, 3
Output high voltage (port 0 in external bus
mode), ALE
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
Power supply current (see Figure 21):
Internal reset pull-down resistor
Pin capacitance
Active mode (see Note 5)
Idle mode (see Note 5)
Power-down mode or clock stopped (see Fig-
OL
OL
ure 25 for conditions)
per port pin:
per 8-bit port:
OH1
25 f
OL
I
I
CC(MAX)
CC(MAX)
9
, except when ALE is off then V
amb
for all outputs:
, PSEN
IN
PARAMETER
PARAMETER
10
is approximately 2 V.
= 0 C to +70 C. For T
11
(except EA)
diti
= 0.9
= 0.18
3
CC
test conditions.
OL
)
FREQ. + 1.1 mA
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
FREQ. +1.0 mA; See Figure 21.
15 mA (*NOTE: This is 85 C specification.)
26 mA
71 mA
11
8
3
OL
amb
7, 8
must be externally limited as follows:
= –40 C to +85 C, I
OH
OH
6
on ALE and PSEN to momentarily fall below the V
is the voltage specification.
T
0.45 < V
amb
4.5 V < V
T
amb
CONDITIONS
I
I
I
I
OH
= –40 C to +85 C
V
OL
V
OL
V
V
OH
V
V
See note 4
See note 5
CC
CC
CC
CC
= 0 C to 70 C
IN
IN
SS
23
TEST
= 1.6mA
= 3.2mA
= –3.2mA
IN
= –30 A
= 0.4 V
= 2.0 V
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
CC
< V
= 0 V
TL
< 5.5 V
CC
= –750 A.
2
2
– 0.3
0.2 V
V
V
80C51/87C51/80C52/87C52
0.7 V
CC
CC
OL
–0.5
MIN
OL
–1
40
CC
– 0.7
– 0.7
s of ALE and ports 1 and 3. The noise is due
can exceed these conditions provided that no
CC
+0.9
LIMITS
TYP
CC
3
1
–0.7 specification when the
0.2 V
V
V
CC
CC
MAX
–650
–50
225
0.4
0.4
Product specification
50
75
15
CC
10
+0.5
+0.5
–0.1
UNIT
UNIT
k
pF
V
V
V
V
V
V
V
A
A
A
A
A