P87C52SBPN,112 NXP Semiconductors, P87C52SBPN,112 Datasheet - Page 25

IC 80C51 MCU 8K OTP 40-DIP

P87C52SBPN,112

Manufacturer Part Number
P87C52SBPN,112
Description
IC 80C51 MCU 8K OTP 40-DIP
Manufacturer
NXP Semiconductors
Series
87Cr
Datasheet

Specifications of P87C52SBPN,112

Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR
Number Of I /o
32
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Processor Series
P87C5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1012-5
935253690112
P87C52SBPN
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 87C51, 80C51, 87C52 or 80C52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause
4. Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. For frequencies equal or less than 16 MHz, see 16 MHz
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
T
NOTES:
2000 Aug 07
amb
t
t
t
t
t
t
t
t
t
t
t
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Clock
t
t
t
t
Shift Register
t
t
t
t
t
SYMBOL
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
XHDV
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
damage to Port 0 drivers.
“AC Electrical Characteristics”, page 24.
20 s for power-on or wakeup from power down.
= 0 C to +70 C or –40 C to +85 C, V
FIGURE
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
15, 16
14
14
14
14
14
14
14
14
14
14
14
16
18
18
18
18
17
17
17
17
17
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
High time
Low time
Rise time
Fall time
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
CC
PARAMETER
= 5 V 10%, V
SS
= 0 V
1, 2, 3
25
10t
6t
6t
7t
2t
3t
3t
4t
2t
0.38t
0.38t
t
t
t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
12t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MIN
VARIABLE CLOCK
CLCL
0
0
0
CLCL
CLCL
–25
–25
–25
–100
–100
–30
–25
–130
–25
16 MHz to f
–40
–45
–50
–75
–133
–80
80C51/87C51/80C52/87C52
10t
t
t
8t
9t
CLCL
CLCL
4t
3t
5t
5t
2t
3t
max
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MAX
10
–t
0
–t
5
5
4
–25
–150
–165
+25
CHCX
CLCX
–65
–60
–80
–90
–28
+50
–133
33 MHz CLOCK
MIN
360
167
21
45
82
82
40
45
80
5
5
0
0
0
5
5
0
Product specification
MAX
105
140
167
55
30
70
10
60
32
90
55
5
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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