P87C52SBPN,112 NXP Semiconductors, P87C52SBPN,112 Datasheet - Page 30

• Manufacturer Part Number: P87C52SBPN,112
• Description: IC 80C51 MCU 8K OTP 40-DIP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C52SBPN,112

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1012-5; 935253690112; P87C52SBPN

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. V
3. V
*
Philips Semiconductors
EPROM CHARACTERISTICS
These devices can be programmed by using a modified Improved
Quick-Pulse Programming
in the value used for V
width and number of the ALE/PROG pulses.
The family contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as being manufactured by
Philips.
Table 8 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 26 and 27. Figure 28 shows the
circuit configuration for normal program memory verification.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 26. Note that the device is running with a 4 to 6 MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 26. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 8 are held at the ‘Program
Code Data’ levels indicated in Table 8. The ALE/PROG is pulsed
low 5 times as shown in Figure 27.
To program the encryption table, repeat the 5 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
To program the security bits, repeat the 5 pulse programming
sequence using the ‘Pgm Security Bit’ levels. After one security bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other security bits can still
be programmed.
Note that the EA/V
maximum specified V
glitch above that voltage can cause permanent damage to the
Table 8. EPROM Programming Modes
NOTES:
2000 Aug 07
Read signature
Program code data
Verify code data
Pgm encryption table
Pgm security bit 1
Pgm security bit 2
Pgm security bit 3
Trademark phrase of Intel Corporation.
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while V
12.75 V. Each programming pulse is low for 100 s ( 10 s) and high for a minimum of 10 s.
PP
CC
= 12.75 V 0.25 V.
= 5 V 10% during programming and verification.
MODE
PP
PP
pin must not be allowed to go above the
PP
level for any amount of time. Even a narrow
(programming supply voltage) and in the
algorithm. It differs from older methods
RST
1
1
1
1
1
1
1
PSEN
0
0
0
0
0
0
0
ALE/PROG
0*
0*
0*
0*
0*
1
1
30
internal memory, EA is latched on Reset and all further programming
device. The V
and overshoot.
Program Verification
If security bits 2 and 3 have not been programmed, the on-chip
program memory can be read out for program verification. The
address of the program memory locations to be read is applied to
ports 1 and 2 as shown in Figure 28. The other pins are held at the
‘Verify Code Data’ levels indicated in Table 8. The contents of the
address location will be emitted on port 0. External pull-ups are
required on port 0 for this operation.
If the 64 byte encryption table has been programmed, the data
presented at port 0 will be the exclusive NOR of the program byte
with one of the encryption bytes. The user will have to know the
encryption table contents in order to correctly decode the verification
data. The encryption table itself cannot be read out.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 92H indicates 87C51
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 8, and
which satisfies the timing specifications, is suitable.
Security Bits
With none of the security bits programmed the code in the program
memory can be verified. If the encryption table is programmed, the
code will be encrypted when verified. When only security bit 1 (see
Table 9) is programmed, MOVC instructions executed from external
program memory are disabled from fetching code bytes from the
of the EPROM is disabled. When security bits 1 and 2 are
programmed, in addition to the above, verify mode is disabled.
When all three security bits are programmed, all of the conditions
above apply and all external program memory execution is disabled.
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
EA/V
V
V
V
V
V
1
PP
1
PP
PP
PP
PP
PP
PP
source should be well regulated and free of glitches
80C51/87C51/80C52/87C52
P2.7
0
1
0
1
1
1
0
P2.6
0
0
0
0
1
1
1
P3.7
Product specification
0
1
1
1
1
0
0
PP
is held at
P3.6
0
1
1
0
1
0
1