P87C52SBPN,112 NXP Semiconductors, P87C52SBPN,112 Datasheet - Page 31

• Manufacturer Part Number: P87C52SBPN,112
• Description: IC 80C51 MCU 8K OTP 40-DIP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C52SBPN,112

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1012-5; 935253690112; P87C52SBPN

1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
Philips Semiconductors
Table 9. Program Security Bits for EPROM Devices
NOTES:
2000 Aug 07
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
1
2
3
4
PROGRAM LOCK BITS
ALE/PROG:
ALE/PROG:
SB1
U
P
P
P
SEE EXPLODED VIEW BELOW
SB2
1
0
U
U
P
P
4–6MHz
1, 2
1
0
1
SB3
U
U
U
P
A0–A7
1
1
1
2
PROTECTION DESCRIPTION
No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if
programmed.)
MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM
is disabled.
Same as 2, also verify is disabled.
Same as 3, external execution is disabled. Internal data RAM is not accessible.
5 PULSES
t
GLGH
3
Figure 26. Programming Configuration
= 100 s 10 s
4
Figure 27. PROG Waveform
P1
RST
P3.6
P3.7
XTAL2
XTAL1
V
SS
5
EPROM/OTP
31
1
ALE/PROG
P2.0–P2.5
EA/V
PSEN
V
P2.7
P2.6
CC
PP
P0
t
GHGL
= 10 s MIN
80C51/87C51/80C52/87C52
+5V
SU00875
PGM DATA
+12.75V
5 PULSES TO GROUND
0
1
0
A8–A12
SU00873
Product specification