P87C52SBPN,112 NXP Semiconductors, P87C52SBPN,112 Datasheet - Page 7

• Manufacturer Part Number: P87C52SBPN,112
• Description: IC 80C51 MCU 8K OTP 40-DIP
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C52SBPN,112

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1012-5; 935253690112; P87C52SBPN

Philips Semiconductors
PIN DESCRIPTIONS
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V
2000 Aug 07
V
V
P0.0–0.7
P1.0–P1.7
P2.0–P2.7
P3.0–P3.7
RST
ALE/PROG
PSEN
EA/V
XTAL1
XTAL2
MNEMONIC
SS
CC
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
PP
39–32 43–36
21–28 24–31
10–17
DIP
1–8
20
40
10
11
12
13
14
15
16
17
30
29
31
19
18
1
2
9
PIN NUMBER
13–19
LCC
2–9
11,
22
44
13
14
15
16
17
18
19
10
33
32
35
21
20
11
2
3
40–44,
37–30
18–25
7–13
QFP
1–3
16
38
40
41
10
11
12
13
27
26
29
15
14
5,
5
7
8
9
4
TYPE NAME AND FUNCTION
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
also the program pulse input (PROG) during EPROM programming. ALE can be disabled by
Ground: 0 V reference.
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
Port 0: Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins
that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0
also outputs the code bytes during program verification and received code bytes during
EPROM programming. External pull-ups are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 1 pins that are externally pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: I
receives the low-order address byte during program memory verification. Alternate functions
for Port 1 include:
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: I
the high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2
special function register. Some Port 2 pins receive the high order address bits during
EPROM programming and verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source
current because of the pull-ups. (See DC Electrical Characteristics: I
the special features of the 80C51 family, as listed below:
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
capacitor to V
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
0FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than the on-chip ROM/OTP. This pin also
receives the 12.75 V programming supply voltage (V
security bit 1 is programmed, EA will be internally latched on Reset.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2: Output from the inverting oscillator amplifier.
T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out)
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
CC
.
7
SS
80C51/87C51/80C52/87C52
permits a power-on reset using only an external
CC
+ 0.5 V or V
PP
) during EPROM programming. If
SS
– 0.5 V, respectively.
IL
). Port 3 also serves
Product specification
IL
IL
). Port 1 also
). Port 2 emits