P87C54SBAA,512 NXP Semiconductors, P87C54SBAA,512 Datasheet - Page 24

• Manufacturer Part Number: P87C54SBAA,512
• Description: IC 80C51 MCU 16K OTP 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 87Cr

Specifications of P87C54SBAA,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Processor Series: P87C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-1252-5; 935258650512; P87C54SBAA

The GF3 bit is a general purpose user–defined flag. Note that bit 2 is
Philips Semiconductors
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH)
AUXR.1
AUXR.0
Dual DPTR
The dual DPTR structure (see Figure 13) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them.
Where:
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
not writable and is always read as a zero. This allows the DPS bit to
2000 Aug 07
New Register Name: AUXR1#
SFR Address: A2H
Reset Value: xxxx00x0B
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
7
–
7
–
6
–
Select Reg
6
–
DPTR0
DPTR1
EXTRAM
AO
5
–
5
–
4
–
LPEP
4
(RX+ only)
Turns off ALE output.
3
–
GF3
3
2
–
2
0
DPS
0
1
EXTRAM
1
1
–
AO
DPS
0
0
24
be quickly toggled simply by executing an INC DPTR instruction
without affecting the GF3 or LPEP bits.
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
INC DPTR
MOV DPTR, #data16
MOV A, @ A+DPTR
MOVX A, @ DPTR
MOVX @ DPTR , A
JMP @ A + DPTR
AUXR1
DPS
BIT0
8XC51RA+/RB+/RC+/RD+/80C51RA+
(83H)
DPH
Increments the data pointer by 1
Loads the DPTR with a 16-bit constant
Move code byte relative to DPTR to ACC
Move external RAM (16-bit address) to
ACC
Move ACC to external RAM (16-bit
address)
Jump indirect relative to DPTR
Figure 13.
(82H)
DPL
8XC51FA/FB/FC/80C51FA
DPTR1
DPTR0
Product specification
EXTERNAL
MEMORY
8XC54/58
DATA
SU00745A