LPC1754FBD80,551 NXP Semiconductors, LPC1754FBD80,551 Datasheet - Page 16

• Manufacturer Part Number: LPC1754FBD80,551
• Description: IC ARM CORTEX MCU 128K 80-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1754FBD80,551

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 80-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 6 Channel
• On-chip Dac: 10 bit
• Cpu Family: LPC17xx
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 100MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 52
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.4/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4790; 935287913551

NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
7.7.1 Features
7.7.2 Interrupt sources
7.7 Nested Vectored Interrupt Controller (NVIC)
7.8 Pin connect block
7.9 General purpose DMA controller
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on Port 0 and Port 2 (total of 30 pins) regardless of the selected function, can be
programmed to generate an interrupt on a rising edge, a falling edge, or both.
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or
no resistor enabled.
The GPDMA is an AMBA AHB compliant peripheral allowing selected
LPC1759/58/56/54/52/51 peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral, and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the USB and Ethernet (LPC1758 only) controllers and the various on-chip SRAM areas.
The supported APB peripherals are SSP0/1, all UARTs, the I
and the DAC. Two match signals for each timer can be used to trigger DMA transfers.
Remark: Note that the DAC is not available on the LPC1752/51, and the I
is not available on the LPC1754/52/51.
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Controls system exceptions and peripheral interrupts
In the LPC1759/58/56/54/52/51, the NVIC supports 33 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt (NMI)
Software interrupt generation
All information provided in this document is subject to legal disclaimers.
Rev. 6.01 — 11 March 2011
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
2
S-bus interface, the ADC,
© NXP B.V. 2011. All rights reserved.
2
S-bus interface
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