LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 37
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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UM10237_4
User manual
Masters with the same priority value are scheduled on a round-robin basis.
Table 35.
[1]
Bit
0
2:1
3
7:4
9:8
11:10 -
13:12 EP1
15:14 -
17:16 EP2
31:18 -
Allowed values for nn are: 10 (high priority) and 01 (low priority).
Symbol
scheduler
break_burst
quantum_type
quantum_size
default_master
AHB Arbiter Configuration register 2 (AHBCFG2 - address 0xE01F C18C) bit
description
Rev. 04 — 26 August 2009
Value Description
0
1
00
01
10
11
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
nn
-
nn
-
nn
-
Break all defined length bursts (the CPU does not create
Master 2 (Ethernet) is the default master.
Priority scheduling.
Uniform (round-robin) scheduling.
defined bursts).
Break all defined length bursts greater than four-beat.
Break all defined length bursts greater than eight-beat.
Never break defined length bursts.
A quantum is an AHB clock.
A quantum is an AHB bus cycle.
Controls the type of arbitration and the number of quanta
before re-arbiration occurs.
Preemptive, re-arbitrate after 1 AHB quantum.
Preemptive, re-arbitrate after 2 AHB quanta.
Preemptive, re-arbitrate after 4 AHB quanta.
Preemptive, re-arbitrate after 8 AHB quanta.
Preemptive, re-arbitrate after 16 AHB quanta.
Preemptive, re-arbitrate after 32 AHB quanta.
Preemptive, re-arbitrate after 64 AHB quanta.
Preemptive, re-arbitrate after 128 AHB quanta.
Preemptive, re-arbitrate after 256 AHB quanta.
Preemptive, re-arbitrate after 512 AHB quanta.
Preemptive, re-arbitrate after 1024 AHB quanta.
Preemptive, re-arbitrate after 2048 AHB quanta.
Preemptive, re-arbitrate after 4096 AHB quanta.
Preemptive, re-arbitrate after 8192 AHB quanta.
Preemptive, re-arbitrate after 16384 AHB quanta.
Non- preemptive, infinite AHB quanta.
Reserved.
External priority for master 1 (CPU).
Reserved.
External priority for master 2 (Ethernet).
Reserved. User software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Chapter 3: LPC24XX System control
UM10237
© NXP B.V. 2009. All rights reserved.
37 of 792
Reset
value
1
10
0100
01
-
00
-
NA
0
00
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