LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 511
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
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Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
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UM10237_4
User manual
17.2.1 FullCAN message interrupt enable bit
17.2 FullCAN interrupts
The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a
maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM
is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured to
participate in the interrupt scheme. It is still possible to define more than 64 FullCAN
objects. The only difference is, that the remaining FullCAN objects will not provide a
FullCAN interrupt.
The FullCAN Interrupt Register-set contains interrupt flags (IntPndx) for (pending)
FullCAN receive interrupts. As soon as a FullCAN message is received, the according
interrupt bit (IntPndx) in the FCAN Interrupt Register gets asserted. In case that the Global
FullCAN Interrupt Enable bit is set, the FullCAN Receive Interrupt is passed to the
Vectored Interrupt Controller.
Application Software has to solve the following:
The software that covers the interrupt priority handling has to assign a receive interrupt
priority to every FullCAN object. If more than one interrupt is pending, then the software
has to decide, which received FullCAN object has to be served next.
To each FullCAN object a new FullCAN Interrupt Enable bit (FCANIntxEn) is added, so
that it is possible to enable or disable FullCAN interrupts for each object individually. The
new Message Lost flag (MsgLstx) is introduced to indicate whether more than one
FullCAN message has been received since last time this message object was read by the
CPU. The Interrupt Enable and the Message Lost bits reside in the existing Look-up Table
RAM.
In
FullCAN, Section. The new introduced FullCAN Message Interrupt enable bit can be used
to enable for each FullCAN message an Interrupt.
1. Index/Object number calculation based on the bit position in the FCANIC Interrupt
2. Interrupt priority handling if more than one FullCAN receive interrupt is pending.
Figure 18–83
Register for more than one pending interrupt.
8 FullCAN Identifiers with their Source CAN Channel are defined in the
Rev. 04 — 26 August 2009
Chapter 18: LPC24XX CAN controllers CAN1/2
UM10237
© NXP B.V. 2009. All rights reserved.
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