LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 563
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Price
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Part Number:
LPC2458FET180,551
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6. Register description
UM10237_4
User manual
5.3.16 APB interfaces
5.3.17 Interrupt logic
Table 489. Receive FIFO status flags
The APB interface generates the interrupt and DMA requests, and accesses the MCI
adapter registers and the data FIFO. It consists of a data path, register decoder, and
interrupt/DMA logic. DMA is controlled by the General Purpose DMA controller, see that
chapter for details.
The interrupt logic generates an interrupt request signal that is asserted when at least one
of the selected status flags is HIGH. A mask register is provided to allow selection of the
conditions that will generate an interrupt. A status flag generates the interrupt request if a
corresponding mask flag is set.
The MCI registers are shown in
Table 490. Summary of MCI registers
Symbol
RxFifoFull
RxFifoEmpty
RxHalfFull
RxDataAvlbl
RxOverrun
Name
MCIPower
MCIClock
MCIArgument
MMCCommand Command register.
MCIRespCmd
MCIResponse0 Response register.
MCIResponse1 Response register.
MCIResponse2 Response register.
MCIResponse3 Response register.
MCIDataTimer
MCIDataLength Data control register.
MCIDataCtrl
MCIDataCnt
MCIStatus
MCIClear
Description
Power control register.
Clock control register.
Argument register.
Response command register.
Data Timer.
Data control register.
Data counter.
Status register.
Clear register.
Rev. 04 — 26 August 2009
Set to HIGH when the receive FIFO does not contain valid data.
Set to HIGH when an overrun error occurs. This flag is cleared by writing
Description
Set to HIGH when all 16 receive FIFO words contain valid data.
Set to HIGH when 8 or more receive FIFO words contain valid data. This
flag can be used as a DMA request.
Set to HIGH when the receive FIFO is not empty. This flag is the inverse
of the RxFifoEmpty flag.
to the MCIClear register.
Table
21–490.
Chapter 21: LPC24XX SD/MMC card interface
Access Width Reset
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
RO
WO
8
12
32
11
6
32
32
32
31
32
16
8
16
22
11
Value
0x00
0x000
0x00000000 0xE008 C008
0x000
0x00
0x00000000 0xE008 C014
0x00000000 0xE008 C018
0x00000000 0xE008 C01C
0x00000000 0xE008 C020
0x00000000 0xE008 C024
0x0000
0x00
0x0000
0x000000
-
[1]
UM10237
© NXP B.V. 2009. All rights reserved.
Address
0xE008 C000
0xE008 C004
0xE008 C00C
0xE008 C010
0xE008 C028
0xE008 C02C
0xE008 C030
0xE008 C034
0xE008 C038
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