LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 80
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
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UM10237_4
User manual
Table 71.
[1]
[2]
[3]
Remark: Deep-sleep mode can be entered by setting the deep-sleep mode (DP) bit, the
dynamic memory clock enable bit (CE), and the dynamic clock control bit (CS) to one. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
Bit
2
4:3
5
6
8:7
12:9
13
31:14 -
Clock enable must be HIGH during SDRAM initialization.
The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional
mode set this bit LOW.
Disabling CLKOUT can be performed if there are no SDRAM memory transactions. When enabled this bit
can be used in conjunction with the dynamic memory clock control (CS) field.
Symbol
Self-refresh
request,
EMCSREFREQ
(SR)
-
Memory clock
control (MMC)
-
SDRAM
initialization (I)
-
Low-power
SDRAM
deep-sleep
mode (DP)
Dynamic Control register (EMCDynamicControl - address 0xFFE0 8020) bit
description
Rev. 04 — 26 August 2009
Value Description
0
1
-
0
1
-
00
01
10
11
-
0
1
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Normal mode.
Enter self-refresh mode (POR reset value).
By writing 1 to this bit self-refresh can be entered under
software control. Writing 0 to this bit returns the EMC to
normal mode.
The self-refresh acknowledge bit in the EMCStatus
register must be polled to discover the current operating
mode of the EMC.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
CLKOUT enabled (POR reset value).
CLKOUT disabled.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Issue SDRAM NORMAL operation command (POR
reset value).
Issue SDRAM MODE command.
Issue SDRAM PALL (precharge all) command.
Issue SDRAM NOP (no operation) command)
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Normal operation (POR reset value).
Enter Deep-sleep mode.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
[2]
[3]
UM10237
© NXP B.V. 2009. All rights reserved.
80 of 792
Reset
Value
1
NA
0
NA
00
NA
0
NA
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