LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 82
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
LPC2458FET180,551
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UM10237_4
User manual
10.6 Dynamic Memory Read Configuration register
10.7 Dynamic Memory Percentage Command Period register
(EMCDynamicReadConfig - 0xFFE0 8028)
The EMCDynamicReadConfig register configures the dynamic memory read strategy.
This register must only be modified during system initialization. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Important: Especially it should be highlighted that the default clock delay methodology
requires the output clock to be delayed externally to the chip to avoid hold time issue for
the SDRAM. In most application boards, there will be no such external delay circuit and
the application should write correct value to the EMCDynamicReadConfig register to use
Command Delay Strategy. The Clock Delay Strategy is the default setting on reset!
Table 5–73
Table 73.
(EMCDynamictRP - 0xFFE0 8030)
The EMCDynamicTRP register enables you to program the precharge command period,
tRP. This register must only be modified during system initialization. This value is normally
found in SDRAM data sheets as tRP. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–74
Bit
1:0
31:2
Symbol
Read data
strategy (RD)
-
Dynamic Memory Read Configuration register (EMCDynamicReadConfig -
address 0xFFE0 8028) bit description
shows the bit assignments for the EMCDynamicReadConfig register.
shows the bit assignments for the EMCDynamicTRP register.
Rev. 04 — 26 August 2009
Value Description
00
01
10
11
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Clock out delayed strategy, using CLKOUT (command
not delayed, clock out delayed). POR reset value.
Command delayed strategy, using EMCCLKDELAY
(command delayed, clock out not delayed).
Command delayed strategy plus one clock cycle, using
EMCCLKDELAY (command delayed, clock out not
delayed).
Command delayed strategy plus two clock cycles, using
EMCCLKDELAY (command delayed, clock out not
delayed).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10237
© NXP B.V. 2009. All rights reserved.
82 of 792
Reset
Value
0x0
NA
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