LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 223
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
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- Download datasheet (5Mb)
NXP Semiconductors
Table 190. Back-to-back Inter-packet-gap register (IPGT - address 0xFFE0 0008) bit description
Table 191. Non Back-to-back Inter-packet-gap register (IPGR - address 0xFFE0 000C) bit description
UM10237_4
User manual
Bit
6:0
31:7
Bit
6:0
7
14:8
31:15 -
Symbol
NON-BACK-TO-BACK
INTER-PACKET-GAP PART2
-
NON-BACK-TO-BACK
INTER-PACKET-GAP PART1
Symbol
BACK-TO-BACK
INTER-PACKET-GAP
-
7.1.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0xFFE0 0008)
7.1.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0xFFE0 000C)
7.1.5 Collision Window / Retry Register (CLRT - 0xFFE0 0010)
The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0xFFE0 0008. Its
bit definition is shown in
The Non Back-to-Back Inter-Packet-Gap register (IPGR) has an address of
0xFFE0 000C. Its bit definition is shown in
The Collision window / Retry register (CLRT) has an address of 0xFFE0 0010. Its bit
definition is shown in
Function
This is a programmable field representing the nibble time offset of the minimum
possible period between the end of any transmitted packet to the beginning of the
next. In Full-Duplex mode, the register value should be the desired period in
nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is
0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or
9.6 µs (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d),
which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs
(in 10 Mbps mode).
Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Function
This is a programmable field representing the Non-Back-to-Back
Inter-Packet-Gap. The recommended value is 0x12 (18d), which
represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in
10 Mbps mode).
Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
This is a programmable field representing the optional carrierSense
window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is
detected during the timing of IPGR1, the MAC defers to carrier. If,
however, carrier becomes active after IPGR1, the MAC continues timing
IPGR2 and transmits, knowingly causing a collision, thus ensuring fair
access to medium. Its range of values is 0x0 to IPGR2. The recommended
value is 0xC (12d)
Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Table
Rev. 04 — 26 August 2009
Table
11–192.
11–190.
Table
11–191.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
223 of 792
Reset
value
0x0
0x0
Reset
value
0x0
0x0
0x0
0x0
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