EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 275
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
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- Download datasheet (13Mb)
DS785UM1
8.5.2.2 8 BPP Word Layout
8.5.2.3 16 BPP WORD Layout
For a Block Copy where 4 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
starts at bit 24, etc. The start pixel, P2, is in the word at address 0x0000 and has a beginning
bit position of 16. This makes 16 = 0x10 the value that is used for the SPEL field in the
“SRCPIXELSTRT”
Let the starting SDRAM address of the destination image be 0x0030.
Pixel 2 starts at bit 16, Pixel 3 starts at bit 34, etc. The start pixel, P2, is in the word at address
0x0030 and has a beginning bit position of 16. This makes 16 = 0x10 the value that is used
for the SPEL field in the
The end pixel, P5, is in the word at address 0x0034 and has a beginning bit position of 8. This
makes 8 = 0x8 the value that is used for the EPEL field in the
For a Block Copy where 8 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
starts at bit 16, etc. The start pixel, P0, is in the word at address 0x0000 and has a beginning
bit position of 0. This makes 0 = 0x0 the value that is used for the SPEL field in the
“SRCPIXELSTRT”
Note:The word count for this example would be: 2 - 1 = 1 words, since P5 ends in the 2nd word.
Address
Address
Address
0x000C
0x0000
0x0004
0x0030
0x0034
0x0000
0x0004
0x0008
So, WIDTH = 0x1 would be written to the
31
31
31
Table 8-16. 8 BPP Memory Layout for Destination Image
register.
register.
Table 8-17. 16 BPP Memory Layout for Source Image
Table 8-15. 8 BPP Memory Layout for Source Image
P3
P7
P3
P7
“DESTPIXELSTRT”
24 23
24 23
P1
P3
P5
P7
Copyright 2007 Cirrus Logic
P2
P6
P2
P6
Table 8-15
Table 8-17
“BLKDESTWIDTH”
register.
16 15
16 15
16 15
shows that Pixel 2 starts at bit 16, Pixel 3
shows that Pixel 0 starts at bit 0, Pixel 1
P1
P5
P1
P5
“DESTPIXELSTRT”
register.
8 7
8 7
P0
P2
P4
P6
Table 8-16
P0
P4
P0
P4
Graphics Accelerator
EP93xx User’s Guide
0
0
0
shows that
register.
8-11
8
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