EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 418
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
- Current page: 418 of 824
- Download datasheet (13Mb)
10
10-24
DMA Controller
EP93xx User’s Guide
NOTE: The naming convention used for channels and ports is as follows - even numbers
correspond to transmit channels/ports and odd numbers correspond to receive
channels/ports.
PPALLOC[3:0]
M2P Channel
Ch 1, 3, 5, 7, 9
PPALLOC[3:0]
Ch 0, 2, 4, 6, 8
other values
other values
0000
0001
0010
0100
0101
1000
1001
0011
0110
0111
Table 10-5. PPALLOC Register Bits Decode for a Transmit Channel
0000
0001
0010
0100
0101
1000
1001
0011
0110
0111
Table 10-6. PPALLOC Register Bits Decode for a Receive Channel
0
1
2
3
4
5
6
7
8
9
Table 10-7. PPALLOC Register Reset Values
Copyright 2007 Cirrus Logic
PPALLOC[3:0]
Port allocated
Port allocated
0000
0000
0001
0001
0010
0010
0100
0100
0011
0011
PORT 10
PORT 12
PORT 14
PORT 16
PORT 18
not used
PORT 0
PORT 2
PORT 4
PORT 6
PORT 8
PORT 13
PORT 15
PORT 17
PORT 19
PORT 11
not used
PORT 1
PORT 3
PORT 5
PORT 7
PORT 9
Port allocated on reset
Peripheral Allocated
Peripheral Allocated
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 8
PORT 9
UART1 Tx
UART2 Tx
UART3 Tx
AAC2 Tx
AAC1 Tx
AAC3 Tx
I2S1 Tx
I2S2 Tx
I2S3 Tx
IrDA Tx
UART1 Rx
UART2 Rx
UART3 Rx
AAC1 Rx
AAC2 Rx
AAC3 Rx
I2S1 Rx
I2S2 Rx
I2S3 Rx
IrDA Rx
DS785UM1
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