EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 429
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
- Current page: 429 of 824
- Download datasheet (13Mb)
INTERRUPT
DS785UM1
31
15
Address:
30
14
29
13
28
12
NFBIntEn:
RSS:
NO_HDSK:
PWSC:
Channel Base Address + 0x0004 - Read/Write
27
11
26
10
Copyright 2007 Cirrus Logic
RSVD
25
9
Setting this bit to “1” enables the generation of the NFB
interrupt in the DMA_BUF_ON state of the DMA channel
buffer state machine. Setting this bit to zero disables
generation of the NFB Interrupt. Normally when the
channel is enabled, this bit should be 1. However in the
case where the current buffer is the last, then this bit can
be cleared to prevent the generation of an interrupt while
the DMA State machine is in the DMA_BUF_ON state.
Request Source Selection.
00 - External DReq.
01 - Internal SSPRx.
10 - Internal SSPTx.
11 - Internal IDE.
When set, the peripheral doesn’t require the regular
handshake protocol. This is optional for external DMAs,
but this bit needs to be set for SSP and IDE operations.
Setting this bit will imply the use of a wait state counter
that will mask hardware requests after each DMA write.
Peripheral Wait States Count. Gives the latency (in HCLK
cycles) needed by the peripheral to de-assert its request
line once the M2M transfer is finished.During this latency
period, the DMA channel will not consider any request.
This wait state count is triggered after each peripheral
width transfer, right after the DMA write phase.In the case
of internal DMA, this means that the count will start when
the DMA has had confirmation from AHB that the write is
accepted and done. In the case of an external DMA that
doesn’t use a handshaking protocol, the count will start
when the DMA has received the acknowledge of the write
from the SMC.If the acknowledge from the SMC takes too
long to arrive, the processor can still cancel the counter
stall by writing the CONTROL register.
24
8
RSVD
23
7
22
6
21
5
20
4
19
3
EP93xx User’s Guide
NFBint
18
2
DMA Controller
DONEInt
17
1
STALLInt
10-35
16
0
10
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