EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 529
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
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- Download datasheet (13Mb)
DS785UM1
14.2.3 Interrupts
14.2.3.1 UARTMSINTR
14.2.3.2 UARTRXINTR
14.2.3.3 UARTTXINTR
There are five interrupts generated by the UART. Four of these are individual maskable active
HIGH interrupts:
The interrupts are also output as a combined single interrupt UARTINTR.
Each of the four individual maskable interrupts is enabled or disabled by changing the mask
bits in UARTCR. Setting the appropriate mask bit HIGH enables the interrupt.
The transmit and receive dataflow interrupts UARTRXINTR and UARTTXINTR have been
separated from the status interrupts. This allows UARTRXINTR and UARTTXINTR to be
used in a DMA controller, so that data can be read or written in response to just the FIFO
trigger levels. The status of the individual interrupt sources can be read from UARTIIR.
The modem status interrupt is asserted if any of the modem status lines (nUARTCTS,
nUARTDCD and nUARTDSR) change. It is cleared by writing to the UART1IntIDIntClr
register.
This interrupt is not independently connected to the system interrupt controller.
The receive interrupt changes state when one of the following events occurs:
If the FIFOs are enabled and the receive FIFO is half or more full (it contains eight or more
words), then the receive interrupt is asserted HIGH. The receive interrupt is cleared by
reading data from the receive FIFO until it becomes less than half full.
If the FIFOs are disabled (have a depth of one location) and data is received thereby filling
the location, the receive interrupt is asserted HIGH. The receive interrupt is cleared by
performing a single read of the receive FIFO.
This interrupt is connected to the system interrupt controller.
The transmit interrupt changes state when one of the following events occurs:
• UARTMSINTR
• UARTRXINTR
• UARTRTINTR
• UARTTXINTR
• If the FIFOs are enabled and the transmit FIFO is at least half empty (it has space for
eight or more words), then the transmit interrupt is asserted HIGH. It is cleared by filling
the transmit FIFO to more than half full.
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
14-7
14
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