EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 720
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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- EP9307-CRZ PDF datasheet #3
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- Download datasheet (13Mb)
23
23-8
Synchronous Serial Port
EP93xx User’s Guide
23.5.9 Motorola SPI Format with SPO=1, SPH=0
SFRMOUT /
SCLKOUT /
SFRMIN
Single and continuous transmission signal sequences for Motorola SPI format with SPO=1,
SPH=0 are shown in
In this configuration, during idle periods
SCLKIN
SSPRXD
SSPTXD
Note: In
SSPOE
• the SCLKOUT signal is forced HIGH
• SFRMOUT is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling
• when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling
SSPOE (=0)
SFRMOUT /
SCLKOUT /
the SCLKOUT pad (active LOW enable)
the SCLKOUT pad (active LOW enable).
SSPTXD /
SSPRXD
SCLKIN
SFRMIN
Figure 23-6. Motorola SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
Figure
Figure 23-7. Motorola SPI Frame Format (Continuous Transfer)
23-6, Q is an undefined signal.
LS B
MS B
MS B
Figure 23-6
Copyright 2007 Cirrus Logic
MS B
with SPO=1 and SPH=0
and
Figure
4 t o 16 bi t s
4 t o 16 bi t s
23-7.
LSB
MS B
LS B
LS B
DS785UM1
Q
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