EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 80
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
- Current page: 80 of 824
- Download datasheet (13Mb)
3
3-10
MaverickCrunch Co-Processor
EP93xx User’s Guide
3.3 DSPSC Register
63
47
31
15
V
Default:
Definition:
Bit Descriptions:
FWDEN
62
46
30
14
DAID
Invalid
61
45
29
13
mov
Denorm
0x0000_0000_0000_0000
MaverickCrunch Status and Control Register. Accessed only via the
MaverickCrunch instruction set. All bits, including status bits, are both
readable and writable. This register should generally be written only using a
read-modify-write sequence.
RSVD:
INST:
60
44
28
12
sub
cfstrs
sub
subs
bne
HVID
cfldrs
cfmuls
cfadds
subs
bne
pc, lr
59
43
27
11
RM[1:0]
r0, r3
c0, [r0], #4
r2, r3
r1, r1, #4
outer_loop
58
42
26
10
c3, [r2], #4
c1, c2, c3
c0, c0, c1
r12, r12, #4
inner_loop
Copyright 2007 Cirrus Logic
IXE
57
41
25
9
Reserved. Unknown During Read.
Exception Instruction. Whenever an unmasked exception
occurs, these 32 bits are loaded with the instruction that
caused the exception. Hence, this contains the instruction
that caused the most recent unmasked exception.
RSVD
UFE
56
40
24
8
INST
INST
ISAT
OFE
55
39
23
7
RSVD
54
38
22
UI
; branch if j != 0
; branch if n != 0
6
; c1 = c2 * c3;
; sum += c1;
; j -= 4;
; c3 = *filter++;
; *data++ = sum;
; n -= 4;
IOE
INT
53
37
21
5
; return to caller
; data -= m * 4;
; filter -= m * 4;
AEXC
52
36
20
IX
4
UF
51
35
19
3
SAT[1:0]
50
34
18
OF
2
RSVD
49
33
17
1
FCC[1:0]
DS785UM1
48
32
16
IO
0
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