PXAS37KBA,512 NXP Semiconductors, PXAS37KBA,512 Datasheet - Page 12

IC XA MCU 16BIT 32K OTP 68-PLCC

PXAS37KBA,512

Manufacturer Part Number
PXAS37KBA,512
Description
IC XA MCU 16BIT 32K OTP 68-PLCC
Manufacturer
NXP Semiconductors
Series
XAr
Datasheet

Specifications of PXAS37KBA,512

Core Processor
XA
Core Size
16-Bit
Speed
30MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PXAS3x
Core
80C51
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-3536-5
935262377512
PXAS37KBA

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Manufacturer
Quantity
Price
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*
# SFRs are modified from or added to XA-G3 SFRs.
1. At reset, the BCR is loaded with the binary value 00000a11, where “a’ is the value on the BUSW pin. This defaults the address bus size to 24 bits.
2. SFR is loaded from the reset vector.
3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.
4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the
6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes.
7. The RSTSRC register reflects the cause of the last XA-S3 reset. One bit will be set to 1, the others will be cleared to 0.
8. The XA guards writes to certain bits (typically interrupt flags) that may be altered directly by a peripheral function. This prevents loss of an
9. The XA-S3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide . All SFR accesses must be 8-bit operations. Attempts
Philips Semiconductors
NOTES:
2000 Dec 01
S1ADEN
SCR
SSEL*
SWE
SWR*
T2CON*
T2MOD*
TH2
TL2
T2CAPH
T2CAPL
TCON*
TH0
TH1
TL0
TL1
TMOD
TSTAT*
WDCON*
WDL
WFEED1
WFEED2
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
NAME
SFRs are bit addressable.
purposes in future XA derivatives. The reset value shown for these bits is 0.
condition found on the EA pin. Thus, all PnCFGA registers will contain FF, and PnCFGB register will contain 00 when the XA begins
execution using internal code memory. When the XA begins execution using external code memory, the default configuration for pins that
are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference.
interrupt or other status if a bit was written directly by a peripheral action during the time between the read and write portions of an
instruction that performs a read-modify-write operation. Examples of such instructions are:
XA-S3 SFR bits that are guarded in this manner are: ADINT (in ADCON); CF, CCF4, CCF3, CCF2, CCF1, and CCF0 (in CCON); SI (in
I2CON); TI_0 and RI_0 (in S0CON); TI_1 and RI_1 (in S1CON); FE0, BR0, and OE0 (in S0STAT); FE1, BR1, and OE1 (in S1STAT); TF2 (in
T2CON); TF1, TF0, IE1, and IE0 (in TCON); and WDTOF (in WDCON).
to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.
2
C, 2 UARTs, 16 MB address range
Serial port 1 address enable
System configuration register
Segment selection register
Software interrupt enable
Software interrupt request
Timer 2 control register
Timer 2 mode control
Timer 2 high byte
Timer 2 low byte
Timer 2 capture, high byte
Timer 2 capture, low byte
Timer 0 and 1 control register
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
Timer 0 and 1 mode control
Timer 0 and 1 extended status
Watchdog control register
Watchdog timer reload
Watchdog feed 1
Watchdog feed 2
DESCRIPTION
and
clr
setb
s0con,#$fb
tr0
ti_0
Address
SFR
45C
45D
466
440
403
47A
42A
418
419
459
458
45B
45A
410
451
453
450
452
41F
45F
45E
411
ESWEN
PEW2
GATE
MSB
2C7
TF2
2CF
TF1
2FF
21F
357
287
28F
R6SEG
SWR7
SWE7
PRE1
EXF2
2CE
21E
2C6
TR1
28E
2FE
356
286
C/T
12
BIT FUNCTIONS AND ADDRESSES
R5SEG
RCLK0
RCLK1
SWE6
SWR6
PRE0
2CD
2FD
21D
2C5
TF0
28D
355
285
M1
R4SEG
TCLK0
TCLK1
SWE5
SWR5
2CC
21C
2C4
TR0
28C
2FC
354
284
M0
R3SEG
SWR4
EXEN2
SWE4
GATE
2CB
PT1
21B
2C3
28B
2FB
353
283
IE1
WDRUN
R2SEG
SWE3
SWR3
T1OE
PT0
2C2
TR2
2CA
21A
352
282
28A
2FA
C/T
IT1
R1SEG
WDTOF
SWE2
SWR2
T2OE
C/T2
2C1
2C9
219
351
281
289
2F9
CM
IE0
M1
Preliminary specification
R0SEG
CP/RL2
SWE1
SWR1
DCEN
T0OE
LSB
2C0
2C8
2F8
218
350
280
288
IT0
M0
PZ
XA-S3
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Note 6
00h
xx
xx
Reset
Value