PXAS37KBA,512 NXP Semiconductors, PXAS37KBA,512 Datasheet - Page 17

IC XA MCU 16BIT 32K OTP 68-PLCC

PXAS37KBA,512

Manufacturer Part Number
PXAS37KBA,512
Description
IC XA MCU 16BIT 32K OTP 68-PLCC
Manufacturer
NXP Semiconductors
Series
XAr
Datasheet

Specifications of PXAS37KBA,512

Core Processor
XA
Core Size
16-Bit
Speed
30MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PXAS3x
Core
80C51
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-3536-5
935262377512
PXAS37KBA

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Philips Semiconductors
A/D Accuracy
The XA-S3 A/D in 10 -bit mode is specified with 16 samples
averaged in order to factor out on-chip noise. In an application
where averaging 16 samples is not practical, the accuracy
specifications may be de-rated according to the number of samples
2000 Dec 01
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
I2CON
Bit Addressable
Reset Value: 00h
2
C, 2 UARTs, 16 MB address range
BIT
I2CON.7
I2CON.6
I2CON.5
I2CON.4
I2CON.3
I2CON.2
I2CON.1
I2CON.0
1.50
1.25
1.00
0.75
0.50
0.25
0.00
Address:42Ch
1
SYMBOL
CR2
ENA
STA
STO
SI
AA
CR1
CR0
(Pertains to 10-bit mode only. Note that 10-bit mode is only specified up to f
2
3
4
FUNCTION
I
Enable I
Start flag. Setting STA to 1 causes the I
generating a Start condition.
Stop flag. Setting STO to 1 causes the I
Serial Interrupt. SI is set by the I
software needs to respond. SI causes an I
Assert Acknowledge. Setting AA to 1 causes the I
acknowledge pulses for various conditions (see text).
I
I
Figure 5. A/D accuracy by number of averaging samples
2
2
2
MSB
C Rate Control, with CR1 and CR0. See text and table.
C Rate Control, with CR2 and CR0. See text and table.
C Rate Control, with CR2 and CR1. See text and table.
CR2
5
2
C port. When ENA = 1, the I
Figure 6. I
ENA
6
Number of Samples
2
C Control Register (I2CON)
7
STA
17
8
2
STO
C hardware when a new I
that are actually taken. The graph in Figure 5 shows the relationship
of additional A/D error to the number of samples that are averaged.
For example, if a single A/D reading is used with no averaging, the
A/D accuracy should be de-rated by 1.25 LSB.
2
9
C port is enabled.
2
2
C interface to attempt to gain mastership of the bus by
C interface to attempt to generate a Stop condition.
2
C interrupt if enabled and of sufficient priority.
SI
10
2
C hardware to automatically generate
AA
11
2
C state is entered, indicating that
12
CR1
C
= 20 MHz.)
13
CR0
LSB
14
Preliminary specification
15
SU01227
SU00941
XA-S3
16