PXAS37KBA,512 NXP Semiconductors, PXAS37KBA,512 Datasheet - Page 19

IC XA MCU 16BIT 32K OTP 68-PLCC

PXAS37KBA,512

Manufacturer Part Number
PXAS37KBA,512
Description
IC XA MCU 16BIT 32K OTP 68-PLCC
Manufacturer
NXP Semiconductors
Series
XAr
Datasheet

Specifications of PXAS37KBA,512

Core Processor
XA
Core Size
16-Bit
Speed
30MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PXAS3x
Core
80C51
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-3536-5
935262377512
PXAS37KBA

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Manufacturer
Quantity
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Manufacturer:
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1. The XA-S3 I
2. The timer 1 overflow is used to clock the I
Philips Semiconductors
CR0, CR1, and CR2, the Clock Rate Bits
These three bits determine the serial clock frequency when the I
interface is in a master mode. An I
typical and can be derived from many oscillator frequencies. The
various serial rates are shown in Table 4. A variable bit rate may
also be used if Timer 1 is not required for any other purpose while
the I
Table 4 are unimportant when the I
In the slave modes, the hardware will automatically synchronize with
the incoming clock frequency.
Table 4. I
NOTES:
2000 Dec 01
0h (0000)
1h (0001)
2h (0010)
3h (0011)
4h (0100)
5h (0101)
6h (0110)
7h (0111)
Frequency Select
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
(CR2, CR1, CR0)
may be used with care where higher rates are required by the application.
2
2
C, 2 UARTs, 16 MB address range
C hardware is in a master mode. The frequencies shown in
q
2
y
C Rate Control
2
C interface does not conform to the 400kHz I
Clock Divisor
Clock Divisor
(Timer 1)
160
272
352
20
40
68
88
2
2
C rate of 100kHz or lower is
C hardware is in a slave mode.
2
(Timer 1)
(116.65)
2
C interface. The resulting bit rate is 1/2 of the timer overflow rate.
8 MHz
(400)
(200)
90.91
29.41
22.73
50
1
1
1
2
(Timer 1)
2
(176.46)
(136.36)
C specification (which applies to rates greater than 100kHz) in all details, but
12 MHz
(300)
44.12
34.09
2
Example I
C
75
1
1
1
2
19
2
contains F8H, no relevant state information is available and no serial
The I
I2STA is an 8-bit read-only special function register. The three least
significant bits are always zero. The five most significant bits contain
the status code. There are 26 possible status codes. When I2STA
interrupt is requested. All other I2STA values correspond to defined
hardware interface states. When each of these states is entered, a
serial interrupt is requested (SI = “1”).
NOTE: A detailed I
information, including example driver code, will be provided in
a separate document.
C Rates at Specific Oscillator Frequencies
(Timer 1)
(235.29)
(181.82)
16 MHz
(400)
58.82
45.45
2
100
C Status Register, I2STA
1
1
1
2
2
(Timer 1)
C interface description and usage
(294.12)
(227.27)
20 MHz
(125)
73.53
56.82
1
1
1
2
(Timer 1)
(352.94)
(272.73)
24 MHz
(150)
88.24
68.18
Preliminary specification
1
1
1
2
XA-S3
(Timer 1)
(340.91)
(110.29)
(187.5)
30 MHz
85.23
1
1
1
2