STM8S105K4T6C STMicroelectronics, STM8S105K4T6C Datasheet - Page 19

MCU 16KB FLASH MEM 16MHZ 32-LQFP

STM8S105K4T6C

Manufacturer Part Number
STM8S105K4T6C
Description
MCU 16KB FLASH MEM 16MHZ 32-LQFP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet

Specifications of STM8S105K4T6C

Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
STM8S10x
Core
STM8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
25
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STICE-SYS001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
A/d Bit Size
10 bit
A/d Channels Available
7
Height
1.4 mm
Length
7 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.95 V
Width
7 mm
For Use With
497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8947
STM8S105K4T6C

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STM8S105xx
4.14.2
Asynchronous communication (UART mode)
Synchronous communication
LIN master mode
LIN slave mode
SPI
LIN master mode
LIN slave mode
Full duplex communication - NRZ standard format (mark/space)
Programmable transmit and receive baud rates up to 1 Mbit/s (f
following any standard baud rate regardless of the input frequency
Separate enable bits for transmitter and receiver
Two receiver wakeup modes:
-
-
Transmission error detection with interrupt generation
Parity control
Full duplex synchronous transfers
SPI master operation
8-bit data communication
Maximum speed: 1 Mbit/s at 16 MHz (f
Emission: Generates 13-bit synch break frame
Reception: Detects 11-bit break frame
Autonomous header handling - one single interrupt per valid message header
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
Synch delimiter checking
11-bit LIN synch break detection - break detection always active
Parity check on the LIN identifier field
LIN error management
Hot plugging support
Maximum speed: 8 Mbit/s (f
Full duplex synchronous transfers
Simplex synchronous transfers on two lines with a possible bidirectional data line
Master or slave operation - selectable by hardware or software
CRC calculation
1 byte Tx and Rx buffer
Slave/master selection input pin
Address bit (MSB)
Idle line (interrupt)
DocID14771 Rev 10
MASTER
/2) both for master and slave
CPU
/16)
CPU
/16) and capable of
Product overview
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