ST72F324LJ2T5 STMicroelectronics, ST72F324LJ2T5 Datasheet - Page 127
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ST72F324LJ2T5
Manufacturer Part Number
ST72F324LJ2T5
Description
IC MCU 8BIT 8K FLASH 44-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST72F324LJ2T5.pdf
(154 pages)
Specifications of ST72F324LJ2T5
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-10°C ~ 85°C
Package / Case
44-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 10 C
On-chip Adc
10 bit, 12 Channel
For Use With
497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-8242
ST72F324LJ2T5
ST72F324LJ2T5
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Company
Part Number
Manufacturer
Quantity
Price
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STMicroelectronics
Quantity:
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12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Figure 73. Typical Application with RESET pin
Notes:
1. Data guaranteed by design, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I
(I/O ports and control pins) must not exceed I
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (watchdog).
7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current source on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
t
w(RSTL)out
t
t
Symbol
h(RSTL)in
g(RSTL)in
Required
EXTERNAL
R
CIRCUIT
V
V
V
V
I
hys
IO
ON
RESET
OL
IL
IH
IL
USER
max. level specified in
IO
current sunk must always respect the absolute maximum rating specified in
5)
Recommended
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
Output current on RESET pin when
driven low internally
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
INJ(RESET)
in
V
DD
Parameter
Section 12.2.2 on page
0.01µF
0.01µF
Section 12.9.1
1)
5)
1)
1)
V
h(RSTL)in
DD
4.7kΩ
4)
VSS
. Otherwise the reset will not be taken into account internally.
2)
can be ignored.
.
111.
DD
Flash versions
ROM versions
Flash versions
ROM versions
I
V
Internal reset sources
IO
V
, f
DD
DD
=+2mA
CPU
=3V
6)7)8)
R
Conditions
ON
, and T
Filter
A
unless otherwise specified.
GENERATOR
0.85xV
0.7xV
PULSE
Min
2.5
50
13
DD
DD
Section 12.2.2
Typ
2.5
0.3
200
82
30
2
WATCHDOG RESET
0.16xV
0.3xV
and the sum of I
Max
ST72324Lxx
150
72
0.7
INTERNAL
RESET
1)
DD
DD
ST72XXX
127/154
Unit
mA
kΩ
µs
µs
ns
V
V
IO
1