STM32F100VBT6B STMicroelectronics, STM32F100VBT6B Datasheet - Page 20
STM32F100VBT6B
Manufacturer Part Number
STM32F100VBT6B
Description
MCU 32BIT 128K FLASH 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Specifications of STM32F100VBT6B
Featured Product
STM32 Value Line
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
STM32F100x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
6
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
STM32100B-EVAL
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
STM32100B-EVAL - EVAL BOARD FOR STM32F100VBT6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-10659
STM32F100VBT6B
STM32F100VBT6B
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Description
2.16.6
2.17
2.18
2.19
2.20
20/86
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
●
●
●
●
I
The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32F100xx value line embeds three universal synchronous/asynchronous receiver
transmitters (USART1, USART2 and USART3).
The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware
management of the CTS and RTS signals, they support IrDA SIR ENDEC, the
multiprocessor communication mode, the single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits.
Both SPIs can be served by the DMA controller.
HDMI (high-definition multimedia interface) consumer
electronics control (CEC)
The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware
support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI
standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead.
²
C bus
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0.
Programmable clock source
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Doc ID 16455 Rev 5