ST62T25CB6 STMicroelectronics, ST62T25CB6 Datasheet - Page 32
ST62T25CB6
Manufacturer Part Number
ST62T25CB6
Description
IC MCU 8BIT OTP 4K 28 PDIP
Manufacturer
STMicroelectronics
Series
ST6r
Specifications of ST62T25CB6
Core Processor
ST6
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, WDT
Number Of I /o
20
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 6 V
Data Converters
A/D 16x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.600", 15.24mm)
Processor Series
ST62T2x
Core
ST6
Data Bus Width
8 bit
Data Ram Size
64 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
20
Number Of Timers
1
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, ST622XC-KIT/110, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 8-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-2100-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST62T25CB6
Manufacturer:
ST
Quantity:
310
Company:
Part Number:
ST62T25CB6
Manufacturer:
STMicroelectronics
Quantity:
5
ST6215C ST6225C
6.7 REGISTER DESCRIPTION
INTERRUPT OPTION REGISTER (IOR)
Address: 0C8h — Write Only
Reset status: 00h
Caution: This register is write-only and cannot be
accessed by single-bit operations (SET, RES,
DEC,...).
Bit 7 =Reserved, must be cleared.
Bit 6 = LES Level/Edge Selection bit.
0: Falling edge sensitive mode is selected for inter-
Table 7. Interrupt Mapping
32/105
1
rupt vector #1
Vector #0
Vector #1
Vector #2
Vector #3
Vector #4
7
-
number
Vector
LES
Port A
Port B, C
TIMER
ESB
RESET
NMI
ADC
Source
Block
GEN
Reset
Non Maskable Interrupt
Ext. Interrupt Port A
Ext. Interrupt Port B, C
Timer underflow
End Of Conversion
-
Description
-
NOT USED
-
0
-
Register
ADCR
TSCR
Label
N/A
N/A
N/A
N/A
1: Low level sensitive mode is selected for inter-
Bit 5 = ESB Edge Selection bit.
0: Falling edge mode on interrupt vector #2
1: Rising edge mode on interrupt vector #2
Bit 4 = GEN Global Enable Interrupt.
0: Disable all maskable interrupts
1: Enable all maskable interrupts
Note: When the GEN bit is cleared, the NMI inter-
rupt is active but cannot be used to exit from STOP
or WAIT modes.
Bits 3:0 = Reserved, must be cleared.
rupt vector #1
EOC
Flag
TMZ
N/A
N/A
N/A
N/A
STOP
from
Exit
yes
yes
yes
yes
yes
no
FFCh-FFDh
FFAh-FFBh
FFEh-FFFh
FF8h-FF9h
FF6h-FF7h
FF4h-FF5h
FF2h-FF3h
FF0h-FF1h
Address
Vector
Priority
Highest
Priority
Lowest
Priority
Order