EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet

IC ACCLAIM MCU 128KB 100LQFP

EZ80F92AZ020EG

Manufacturer Part Number
EZ80F92AZ020EG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F92AZ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-3871
EZ80F92AZ020EG

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EZ80F92AZ020EG
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EZ80F92AZ020EG
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®
eZ80Acclaim!
Flash Microcontrollers
eZ80F92/eZ80F93
Product Specification
PS015313-0508
Copyright ©2008 by Zilog, Inc. All rights reserved.
www.zilog.com

EZ80F92AZ020EG Summary of contents

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... Flash Microcontrollers eZ80F92/eZ80F93 Product Specification PS015313-0508 Copyright ©2008 by Zilog, Inc. All rights reserved. www.zilog.com ...

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... Zilog is a registered trademark of Zilog, Inc. in the United States and in other countries. eZ80Acclaim!, eZ80, and Z80 are trademarks or registered trademarks of Zilog Inc. All other product or service names are the property of their respective owners. ...

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... Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links given in the table below. Revision Date Level Section May 2008 13 Zilog Debug Interface, Supported Figure 37 Typical ZDI Debug Setup May 2007 12 Electrical Characteristics ...

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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Data Transfer Procedure with SPI Configured as the Master . . . . . . . . . . . . . . . . 135 Data Transfer Procedure with SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . 135 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Serial I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Transferring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Zilog Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 PS015313-0508 Product Specification v Table of Contents ...

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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... External Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 External System Clock Driver (PHI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Zilog Debug Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 PS015313-0508 Product Specification vii Table of Contents ...

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... Architectural Overview Zilog’s eZ80F92 device is a high-speed single-cycle instruction-fetch microcontroller with a maximum clock speed of 20 MHz the first member of Zilog’s new eZ80Acclaim! product family, which offers on-chip Flash program memory. The eZ80F92 device can operate in Z80 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80F92 device makes it suitable for a variety of applications including industrial control, embedded communica- tion, and point-of-sale terminals ...

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Watchdog Timer (WDT) • 24 bits of General-Purpose I/O and ZDI debug interfaces • 100-pin LQFP package • 3.0–3.6 V supply voltage with 5 V tolerant inputs • Operating Temperature Range: Standard: 0 ºC to +70 ºC – Extended: ...

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I C SCL Serial Interface SDA SCK SPI Serial SS Parallel Interface MISO MOSI CTS0/1 DCD0/1 DSR0/1 UART Universal DTR0/1 Asynchronous Receiver/ RI0/1 Transmitter (2) RTS0/1 RXD0/1 TXD0/1 IrDA 8-bit General Encoder/ Decoder PS015313-0508 RTC_VDD Real-Time RTC_XIN Clock and ...

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Pin Description Figure 2 displays the pin layout of the eZ80F92 device in the 100-pin LQFP package. Table 1 on page 5 lists the pins and their functions. ADDR0 1 ADDR1 2 ADDR2 3 ADDR3 4 ADDR4 5 ADDR5 6 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device Pin No Symbol Function 1 ADDR0 Address Bus 2 ADDR1 Address Bus 3 ADDR2 Address Bus 4 ADDR3 Address Bus 5 ADDR4 Address Bus PS015313-0508 Signal Direction Description Bidirectional Configured ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 6 ADDR5 Address Bus 7 V Power Supply Ground SS 9 ADDR6 Address Bus 10 ADDR7 Address Bus 11 ADDR8 Address Bus ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 13 ADDR10 Address Bus 14 ADDR11 Address Bus 15 ADDR12 Address Bus 16 ADDR13 Address Bus 17 ADDR14 Address Bus 18 V Power Supply DD ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 20 ADDR15 Address Bus 21 ADDR16 Address Bus 22 ADDR17 Address Bus 23 ADDR18 Address Bus 24 ADDR19 Address Bus PS015313-0508 Signal Direction Description Bidirectional ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 25 ADDR20 Address Bus 26 ADDR21 Address Bus 27 ADDR22 Address Bus 28 ADDR23 Address Bus 29 CS0 Chip Select 0 30 CS1 Chip Select ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 33 V Power Supply Ground SS 35 DATA0 Data Bus 36 DATA1 Data Bus 37 DATA2 Data Bus 38 DATA3 Data Bus ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 45 IORQ Input/Output Request 46 MREQ Memory Request 47 RD Read 48 WR Write 49 INSTRD Instruction Read Indicator 50 WAIT WAIT Request Input, Active ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 54 BUSACK Bus Acknowledge 55 HALT_SLP HALT and SLEEP Indicator 56 V Power Supply Ground SS 58 RTC_X Real-Time IN Clock Crystal ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 67 V Power Supply DD 68 PD0 GPIO Port D TxD0 UART Transmit Data IR_TxD IrDA Transmit Data 69 PD1 GPIO Port D RxD0 Receive ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 71 PD3 GPIO Port D CTS0 Clear To Send Input, Active Low 72 PD4 GPIO Port D DTR0 Data Terminal Ready 73 PD5 GPIO Port ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 75 PD7 GPIO Port D RI0 Ring Indicator Input, Active Low 76 PC0 GPIO Port C TxD1 Transmit Data Output 77 PC1 GPIO Port C ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 78 PC2 GPIO Port C RTS1 Request To Send 79 PC3 GPIO Port C CTS1 Clear To Send Input, Active Low 80 PC4 GPIO Port ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 82 PC6 GPIO Port C DCD1 Data Carrier Detect 83 PC7 GPIO Port C RI1 Ring Indicator Input, Active Low 84 V Ground SS 85 ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 88 PB0 GPIO Port B T0_IN Timer PB1 GPIO Port B T1_IN Timer PB2 GPIO Port B SS Slave ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 92 PB4 GPIO Port B T4_OUT Timer 4 Out 93 PB5 GPIO Port B T5_OUT Timer 5 Out 94 PB6 GPIO Port B MISO Master ...

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Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued) Pin No Symbol Function 96 V Power Supply Ground SDA I C Serial Data Bidirectional 2 99 SCL I C Serial Clock 100 ...

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Table 2. Pin Characteristics of the eZ80F92 Device (Continued) Pin No Symbol Direction 16 ADDR13 I/O 17 ADDR14 I ADDR15 I/O 21 ADDR16 I/O 22 ADDR17 I/O 23 ADDR18 I/O 24 ADDR19 I/O ...

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Table 2. Pin Characteristics of the eZ80F92 Device (Continued) Pin No Symbol Direction IORQ I/O 46 MREQ I INSTRD O 50 WAIT I 51 RESET I 52 NMI I ...

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Table 2. Pin Characteristics of the eZ80F92 Device (Continued) Pin No Symbol Direction 71 PD3 I/O 72 PD4 I/O 73 PD5 I/O 74 PD6 I/O 75 PD7 I/O 76 PC0 I/O 77 PC1 I/O 78 PC2 I/O 79 PC3 I/O ...

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Table 2. Pin Characteristics of the eZ80F92 Device (Continued) Pin No Symbol Direction 99 SCL I/O 100 PHI O Note Input Output, I/O = Input and Output Undefined. PS015313-0508 Reset Active Tristate Direction Low/High ...

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Register Map All on-chip peripheral registers are accessed in the I/O address space. All I/O operations employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all I/O operations (ADDR[23:16] = range – 0080h 00FFh not ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 008A TMR3_DR_L TMR3_RR_L 008B TMR3_DR_H TMR3_RR_H 008C TMR4_CTL 008D TMR4_DR_L TMR4_RR_L 008E TMR4_DR_H TMR4_RR_H 008F TMR5_CTL 0090 TMR5_DR_L TMR5_RR_L 0091 TMR5_DR_H TMR5_RR_H 0092 TMR_ISS Watchdog Timer 0093 WDT_CTL 0094 WDT_RR General-Purpose Input/Output ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 00A4 PD_ALT1 00A5 PD_ALT2 Chip Select/Wait State Generator 00A8 CS0_LBR 00A9 CS0_UBR 00AA CS0_CTL 00AB CS1_LBR 00AC CS1_UBR 00AD CS1_CTL 00AE CS2_LBR 00AF CS2_UBR 00B0 CS2_CTL 00B1 CS3_LBR 00B2 CS3_UBR 00B3 CS3_CTL ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic Universal Asynchronous Receiver/Transmitter 0 (UART0) Block 00C0 UART0_RBR UART0_THR UART0_BRG_L 00C1 UART0_IER UART0_BRG_H 00C2 UART0_IIR UART0_FCTL 00C3 UART0_LCTL 00C4 UART0_MCTL 00C5 UART0_LSR 00C6 UART0_MSR 00C7 UART0_SPR Block 00C8 I2C_SAR ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic 00D1 UART1_IER UART1_BRG_H 00D2 UART1_IIR UART1_FCTL 00D3 UART1_LCTL 00D4 UART1_MCTL 00D5 UART1_LSR 00D6 UART1_MSR 00D7 UART1_SPR Low-Power Control 00DB CLK_PPD1 00DC CLK_PPD2 Real-Time Clock 00E0 RTC_SEC 00E1 RTC_MIN 00E2 RTC_HRS 00E3 RTC_DOW ...

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Table 3. Register Map (Continued) Address (hex) Mnemonic Chip Select Bus Mode Control 00F0 CS0_BMC 00F1 CS1_BMC 00F2 CS2_BMC 00F3 CS3_BMC Flash Memory Control Registers 00F5 FLASH_KEY 00F6 FLASH_DATA 00F7 FLASH_ADDR_U Flash Address Upper Byte Register 00F8 FLASH_CTRL 00F9 FLASH_FDIV ...

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CPU Core ® ® The eZ80 is the first 8-bit CPU to support 16 MB linear addressing. Each software module or task under a real-time executive or operating system can operate in Z80 patible (64 KB) mode or full ...

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Reset Reset Operation The Reset controller within the eZ80F92 device provides a consistent reset function for all types of resets that can affect the system. A system reset, referred in this document as RESET, returns the eZ80F92 device to a ...

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V POR V VBO V = 0.0V CC System Clock Oscillator Startup Internal RESET Signal Voltage Brownout Reset If, after program execution begins, the supply voltage (V Brownout threshold (V detects the low supply voltage and initiates the RESET via ...

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POR V VBO Program Execution System Clock Internal RESET Signal Figure 4. Voltage Brownout Reset Operation PS015313-0508 Voltage Brown-out RESET mode T timer delay ANA Product Specification 3.3V CC Program Execution Reset ...

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Low-Power Modes Overview The eZ80F92 device provides a range of power-saving features. The highest level of power reduction is provided by SLEEP mode. The next level of power reduction is provided by the HALT instruction. The lowest level of power ...

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HALT Mode Execution of the CPU’s HALT instruction places the eZ80F92 device into HALT mode. In HALT mode, the operating characteristics are: • Primary crystal oscillator is enabled and continues to operate • The system clock is enabled and continues ...

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Table 4. Clock Peripheral Power-Down Register; (CLK_PPD1 = 00DBh) Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position 7 GPIO_D_OFF 6 GPIO_C_OFF 5 GPIO_B_OFF 4 3 SPI_OFF 2 I2C_OFF 1 UART1_OFF 0 UART0_OFF PS015313-0508 7 ...

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Table 5. Clock Peripheral Power-Down Register 2; (CLK_PPD2 = 00DCh) Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position 7 PHI_OFF 6 5 PRT5_OFF 4 PRT4_OFF 3 PRT3_OFF 2 PRT2_OFF 1 PRT1_OFF 0 PRT0_OFF PS015313-0508 ...

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General-Purpose Input/Output GPIO Overview The eZ80F92 device features 24 General-Purpose Input/Output (GPIO) pins. The GPIO pins are assembled as three 8-bit ports—Port B, Port C, and Port D. All port signals can be configured for use as either inputs or ...

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Table 6. GPIO Mode Selection (Continued) GPIO Px_ALT2 Px_ALT1 Px_DDR Mode Bits7:0 Bits7 ...

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Reserved. This pin produces high-impedance output. GPIO Mode 5— This bit enables a dual edge-triggered interrupt mode. Both a rising and a GPIO Mode 6— falling edge on the pin cause an interrupt request to be sent to the CPU. ...

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Data Bus System Clock GPIO Interrupts Each port pin can be used as an interrupt source. Interrupts can be either level- or edge- triggered. Level-Triggered Interrupts When the port is configured for level-triggered interrupts, the corresponding port pin is tristated. ...

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CPU. Any time a port pin is configured for edge-trig- gered interrupt, writing that pin’s Port x Data register causes a reset of the edge- detected interrupt. The programmer must set ...

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Port x Data Direction Registers In conjunction with the other GPIO Control Registers, the Port x Data Direction registers, listed in Table 8, control the operating modes of the GPIO port pins. See 39 for more information. Table 8. Port ...

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Interrupt Controller The interrupt controller on the eZ80F92 device routes the interrupt request signals from the internal peripherals and external devices (via the GPIO pins) to the CPU. Maskable Interrupts On the eZ80F92 device, all maskable interrupts use the CPU’s ...

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I[7:0], byte is stored at the lower address. When any one or more of the interrupt requests (IRQs) become active, an interrupt request is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit ...

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Table 12. Vectored Interrupt Operation (Continued) Memory ADL MADL Mode Bit Bit Operation ® Z80 Mode 0 1 Read the LSB of the interrupt vector placed on the internal vectored interrupt bus, IVECT[7:0], bus by the interrupting peripheral. • IEF1 ...

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Chip Selects and Wait States The eZ80F92 device generates four Chip Selects for external devices. Each Chip Select may be programmed to access either memory space or I/O space. The Memory Chip Selects can be individually programmed ...

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Memory Chip Select Priority A lower-numbered Chip Select is granted priority over a higher-numbered Chip Select. For example, if the address space of Chip Select 0 overlaps the Chip Select 1 address space, Chip Select 0 is active. Reset States ...

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Table 13. Register Values for Memory Chip Select Example in Figure 6 Chip CSx_CTL[3] CSx_CTL[4] Select CSx_EN CSx_IO CS0 1 0 CS1 1 0 CS2 1 0 CS3 1 0 I/O Chip Select Operation I/O Chip Selects can only be ...

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If all of the foregoing conditions are met to generate an I/O Chip Select, then the following actions occur: • The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low) • IORQ is asserted (driven Low) • Depending upon ...

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An example of WAIT state operation is displayed in Select is configured to provide a single WAIT state. The external peripheral being accessed drives the WAIT pin Low to request assertion of an additional WAIT state. If the WAIT pin ...

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Bus Mode Controller The bus mode controller allows the address and data bus timing and signal formats of the eZ80F92 device to be configured to connect seamlessly with external eZ80 Intel-, or Motorola-compatible devices. Bus modes for each of the ...

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Table 15. Z80 Bus Mode Write States STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the address bus, the associated Chip Select signal is asserted. STATE T2 During State T2, the WR signal ...

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System Clock ADDR[23:0] DATA[7:0] CSx RD WAIT WR MREQ or IORQ Intel Bus Mode TM Chip selects configured for Intel bus mode modify the CPU bus signals to duplicate a four- state memory transfer similar to that found on Intel-style ...

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Bus Mode Signals (Pins) INSTRD RD WR WAIT MREQ IORQ ADDR[23:0] DATA[7:0] Intel Bus Mode (Separate Address and Data Buses) During Read operations with separate address and data buses, the Intel bus mode employs 4 states (T1, T2, T3, ...

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Table 16. Intel Bus Mode Read States (Separate Address and Data Buses (Continued) STATE T3 During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven Low at least one CPU system clock cycle prior ...

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System Clock ADDR[23:0] DATA[7:0] CSx ALE RD READY WR MREQ or IORQ Figure 12. Example: Intel PS015313-0508 WAIT TM Bus Mode Read Timing—Separate Address and Data Buses eZ80F92/eZ80F93 Product Specification 58 T4 Chip Selects and Wait ...

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System Clock ADDR[23:0] DATA[7:0] CSx ALE WR READY RD MREQ or IORQ Figure 13. Example: Intel PS015313-0508 WAIT TM Bus Mode Write Timing—Separate Address and Data Buses eZ80F92/eZ80F93 Product Specification 59 T4 Chip Selects and Wait ...

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Intel TM Bus Mode (Multiplexed Address and Data Bus) During Read operations with multiplexed address and data, the Intel bus mode employs four states (T1, T2, T3, and T4) as listed in Table 18. Intel Bus Mode Read States (Multiplexed ...

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Signal timing for Intel Read operation in ures, each Intel bus mode state is 2 CPU system clock cycles in duration. Figure 15 on page 62 also display the assertion of one wait state ( peripheral. System Clock ADDR[23:0] DATA[7:0] ...

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System Clock ADDR[23:0] DATA[7:0] CSx ALE WR READY RD MREQ or IORQ Figure 15. Example: Intel PS015313-0508 WAIT TM Bus Mode Write Timing—Multiplexed Address and Data Bus eZ80F92/eZ80F93 Product Specification 62 T4 Chip Selects and Wait ...

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Motorola Bus Mode Chip selects configured for Motorola bus mode modify the CPU bus signals to duplicate an eight-state memory transfer similar to that found on Motorola-style microcontrollers. The bus signals (and eZ80F92 I/O pins) are mapped as displayed in ...

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Table 20. Motorola Bus Mode Read States (Continued) STATE S4 During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral signal. If the termination signal is not asserted at least one full CPU clock period ...

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Signal timing for Motorola bus mode is displayed for a Read operation in for a Write operation in mode state is 2 CPU system clock cycles in duration. S0 System Clock ADDR[23:0] DATA[7:0] CSx AS DS R/W DTACK MREQ or ...

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S0 System Clock ADDR[23:0] DATA[7:0] CSx AS DS R/W DTACK MREQ or IORQ Figure 18. Example: Motorola Bus Mode Write Timing Switching Between Bus Modes Each time the bus mode controller must switch from one bus mode to another, there ...

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Chip Select Registers Chip Select x Lower Bound Register For Memory Chip Selects, the Chip Select x Lower Bound register, listed in defines the lower bound of the address range for which the corresponding Memory Chip Select (if enabled) can ...

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Chip Select x Upper Bound Register For Memory Chip Selects, the Chip Select x Upper Bound registers, listed in defines the upper bound of the address range for which the corresponding Chip Select (if enabled) can be active. For I/O ...

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Chip Select x Control Register The Chip Select x Control register, listed in the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip Select 0 Control register is registers is . 00h ...

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Chip Select x Bus Mode Control Register+The Chip Select Bus Mode register, listed in Table 25, configures the Chip Select for eZ80 modes. Changing the bus mode allows the eZ80F92 device to interface to peripherals based on the Z80-, Intel-, ...

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Bit Position [3:0] BUS_CYCLE Notes 1. Setting BUS_CYCLE Intel 2. Use of the external WAIT input pin in Z80 greater than 1. 3. BUS_CYCLE produces no effect in PS015313-0508 Value Description 0000 Not valid. 0001 Each bus ...

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Watchdog Timer Watchdog Timer Overview The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power faults, and other system-level problems which may place the CPU into unsuitable operating states. The eZ80F92 WDT features: • Four programmable time-out periods: ...

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Watchdog Timer Operation Enabling and Disabling the WDT The Watchdog Timer is disabled upon a RESET. To enable the WDT, the application program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the WDT cannot be ...

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If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT asserts an NMI for CPU processing. The NMI_FLAG bit can be polled by the CPU to determine the source of the NMI event. ...

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Bit Position [1:0] WDT_PERIOD Note: *RST_FLAG is only cleared by a non-WDT RESET. Watchdog Timer Reset Register The Watchdog Timer Reset register, listed in Watchdog Timer is reset when an register. Any amount of time can occur between the writing ...

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Programmable Reload Timers Programmable Reload Timers Overview The eZ80F92 device features six Programmable Reload Timers (PRT). Each PRT contains a 16-bit downcounter and a 16-bit reload register. In addition, each PRT features a clock divider with four selectable taps for ...

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Programmable Reload Timer Operation Setting Timer Duration There are three factors to consider when determining Programmable Reload Timer dura- tion—clock frequency, clock divider ratio, and initial count value. Minimum duration of the timer is achieved by loading , because the ...

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CLK CLKEN IOWRN t [7:0] CNTH t [7:0] CNTL IRQ Figure 21.PRT SINGLE PASS Mode Operation Example Table 29. PRT SINGLE PASS Mode Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 4 SINGLE PASS Mode ...

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CLK PRT Clock (Clock 4) IOWRN PRT Count X Value Interrupt Request Figure 22. PRT CONTINUOUS Mode Operation Example Table 30. PRT CONTINUOUS Mode Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 4 CONTINUOUS Mode ...

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Then, when the end-of-count value, rupt service request signal is passed to the CPU. PRT_IRQ is cleared to 0 and the interrupt service request signal is inactivated whenever the CPU reads from the timer control regis- ters, TMRx_CTL. Timer Input ...

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CLK PRT Clock (Clock 4) IOWRN PRT Count X Value Timer Output Figure 23. PRT Timer Output Operation Example Table 31. PRT Timer Out Operation Example Parameter PRT Enabled Reload and Restart Enabled PRT Clock Divider = 4 CONTINUOUS Mode ...

Page 89

Table 32. Timer Control Register(TMR0_CTL = 0080h, TMR1_CTL = 0083h, TMR2_CTL = 0086h, TMR3_CTL = 0089h, TMR4_CTL = 008Ch, or TMR5_CTL = 008Fh) Bit Reset CPU Access Note Read only; R/W = Read/Write. Bit Position Value 7 0 ...

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Timer Data Register—Low Byte This Read Only register returns the Low byte of the current count value of the selected timer. The Timer Data Register—Low Byte, listed operation. Reading the current count value does not affect timer ...

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Table 34. Timer Data Register—High Byte(TMR0_DR_H = 0082h, TMR1_DR_H = 0085h, TMR2_DR_H = 0088h, TMR3_DR_H = 008Bh, TMR4_DR_H = 008Eh, or TMR5_DR_H = 0091h) Bit Reset CPU Access Note Read only. Bit Position Value [7:0] 00h–FFh These bits ...

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Timer Reload Register—High Byte The Timer Reload Register—High Byte, listed in byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set to 1 ...

Page 93

Table 37. Timer Input Source Select Register(TMR_ISS = 0092h) Bit Reset CPU Access Note: R/W = Read/Write. Bit Position [7:6] TMR3_IN [5:4] TMR2_IN [3:2] TMR1_IN PS015313-0508 R/W R/W R/W R/W Value Description 00 The ...

Page 94

TMR0_IN PS015313-0508 00 Timer counts at system clock divided by clock divider. 01 Timer event input is Real-Time Clock source (32 kHz or 50/60 Hz—see Real-Time Clock on page 88 for details). 10 The timer event input is the ...

Page 95

Real-Time Clock Real-Time Clock Overview The Real-Time Clock (RTC) keeps time by maintaining a count of seconds, minutes, hours, day-of-the-week, day-of-the-month, year, and century. The current time is kept in 24-hour format. The format for all count and alarm registers ...

Page 96

Real-Time Clock Alarm The clock can be programmed to generate an alarm condition when the current count matches the alarm set-point registers. Alarm registers are available for seconds, minutes, hours, and day-of-the-week. Each alarm can be independently enabled. To generate ...

Page 97

Write values to the RTC alarm registers to set the appropriate alarm conditions • Write to RTC_CTRL to clear the RTC_UNLOCK bit; clearing the RTC_UNLOCK bit resets and enables the clock divider Real-Time Clock Registers The Real-Time Clock registers ...

Page 98

Real-Time Clock Minutes Register This register contains the current minutes count. See Table 39. Real-Time Clock Minutes Register; (RTC_MIN = 00E1h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if ...

Page 99

Real-Time Clock Hours Register This register contains the current hours count. See Table 40. Real-Time Clock Hours Register; (RTC_HRS = 00E2h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if ...

Page 100

Real-Time Clock Day-of-the-Week Register This register contains the current day-of-the-week count. The RTC_DOW register begins counting at 01h Table 41. Real-Time Clock Day-of-the-Week Register; (RTC_DOW = 00E3h) Bit Reset CPU Access Note Unchanged by RESET Read ...

Page 101

Real-Time Clock Day-of-the-Month Register This register contains the current day-of-the-month count. The RTC_DOM register begins counting at 01h Table 42. Real-Time Clock Day-of-the-Month Register; (RTC_DOM = 00E4h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read ...

Page 102

Real-Time Clock Month Register This register contains the current month count. See Table 43. Real-Time Clock Month Register; (RTC_MON = 00E5h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if ...

Page 103

Real-Time Clock Year Register This register contains the current year count. See Table 44. Real-Time Clock Year Register; (RTC_YR = 00E6h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if ...

Page 104

Real-Time Clock Century Register This register contains the current century count. See Table 45. Real-Time Clock Century Register; (RTC_CEN = 00E7h) Bit Reset CPU Access Note Unchanged by RESET; R/W* = Read Only if RTC locked, Read/Write if ...

Page 105

Real-Time Clock Alarm Seconds Register This register contains the alarm seconds value. See Table 46. Real-Time Clock Alarm Seconds Register; (RTC_ASEC = 00E8h) Bit Reset CPU Access Note Unchanged by RESET; R/W = Read/Write. Binary-Coded-Decimal Operation (BCD_EN = ...

Page 106

Real-Time Clock Alarm Minutes Register This register contains the alarm minutes value. See Table 47. Real-Time Clock Alarm Minutes Register; (RTC_AMIN = 00E9h) Bit Reset CPU Access Note Unchanged by RESET; R/W = Read/Write. Binary-Coded-Decimal Operation (BCD_EN = ...

Page 107

Real-Time Clock Alarm Hours Register This register contains the alarm hours value. See Table 48. Real-Time Clock Alarm Hours Register; (RTC_AHRS = 00EAh) Bit Reset CPU Access Note Unchanged by RESET; R/W = Read/Write. Binary-Coded-Decimal Operation (BCD_EN = ...

Page 108

Real-Time Clock Alarm Day-of-the-Week Register This register contains the alarm day-of-the-week value. See Table 49. Real-Time Clock Alarm Day-of-the-Week Register; (RTC_ADOW = 00EBh) Bit Reset CPU Access Note Unchanged by RESET Read Only; R/W* = Read ...

Page 109

Real-Time Clock Alarm Control Register This register contains alarm enable bits for the Real-Time Clock. The RTC_ACTRL regis- ter is cleared by a RESET. See Table 50. Real-Time Clock Alarm Control Register; (RTC_ACTRL = 00ECh) Bit Reset CPU Access Note: ...

Page 110

CLK_SEL and FREQ_SEL select the RTC clock source. If the 32 kHz crystal option is selected the oscillator is enabled and the internal clock divider is set to divide by 32768. If the power-line frequency option is selected, the prescale ...

Page 111

Universal Asynchronous Receiver/Trans- mitter The UART module implements all of the logic required to support several asynchronous communications protocols. The module also implements two separate 16-byte-deep FIFOs for both transmission and reception. A block diagram of the UART is displayed ...

Page 112

UART Functional Description The UART function implements: • The transmitter and associated control logic • The receiver and associated control logic • The modem interface and associated logic UART Functions The UART function implements: • The transmitter and associated control ...

Page 113

UART Receiver The receiver block controls the data reception from the RxD signal. The receiver ...

Page 114

UART Transmitter Interrupt The transmitter hold register empty interrupt is generated if there is no data available in the hold register. The transmission complete interrupt is generated after the data in the shift register is sent. Both interrupts can be ...

Page 115

UART Recommended Usage The following is the standard sequence of events that occur in the eZ80F92 device using the UART. A description of each follows. • Module reset • Control transfers to configure UART operation • Data transfers Module Reset ...

Page 116

If the interrupt is caused by a receive-data-ready condition, the application alternately reads the UARTx_LSR and UARTx_RBR registers and removes all of the received data bytes. It reads the UARTx_LSR ...

Page 117

Recommended Usage of the Baud Rate Generator The following is the normal sequence of operations that should occur after the eZ80F92 device is powered on to configure the Baud Rate Generator: • Assert and deassert RESET • Set UARTx_LCTL[7] to ...

Page 118

Bit Position [7:0] UART_BRG_L Table 53. UART Baud Rate Generator Register—High Bytes(UART0_BRG_H = 00C1h, UART1_BRG_H = 00D1h) Bit Reset CPU Access Note Read only; R/W = Read/Write. Bit Position [7:0] UART_BRG_H UART Registers After a RESET, all UART ...

Page 119

Table 54. UART Transmit Holding Registers(UART0_THR = 00C0h, UART1_THR = 00D0h) Bit Reset CPU Access Note Write only. Bit Position [7: UART Receive Buffer Register The bits in this register reflect the data received. If ...

Page 120

UART Interrupt Enable Register The UARTx_IER register is used to enable and disable the UART interrupts. The UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H registers. See Table 56. Table 56. UART Interrupt Enable Registers(UART0_IER = 00C1h, UART1_IER ...

Page 121

UART Interrupt Identification Register The Read Only UARTx_IIR register allows the user to check whether the FIFO is enabled and the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL registers. See Table 57. UART Interrupt ...

Page 122

Table 58. UART Interrupt Status Codes (Continued) INSTS Value Priority 001 Fifth 000 Lowest UART FIFO Control Register This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable the FIFO. The UARTx_FCTL registers share the ...

Page 123

Bit Position 1 CLRRXF 0 FIFOEN Note: *Receive FIFO is not enabled during UART Line Control Register This register is used to control the communication control parameters. See Table 60 and Table 60. UART Line Control Registers(UART0_LCTL = 00C3h, UART1_LCTL ...

Page 124

Bit Position FPE 4 EPS 3 PEN [2:0] CHAR Note: *Receive Parity is set to SPACE in MULTIDROP mode. PS015313-0508 Value Description 0 Do not send a BREAK signal. 1 Send Break UART sends continuous zeroes on ...

Page 125

Table 61. UART Character Parameter Definition CHAR[2:0] 000 001 010 011 100 101 110 111 Table 62. Parity Select Definition for Multidrop Communications MDM UARTx_MGTL[ Note: *In MULTIDROP mode, EPS resets to 0 after the first ...

Page 126

UART Modem Control Register This register is used to control and check the modem status, as listed in Table 63. UART Modem Control Registers(UART0_MCTL = 00C4h, UART1_MCTL = 00D4h) Bit Reset CPU Access Note Read Only; R/W = ...

Page 127

UART Line Status Register This register is used to show the status of UART interrupts and registers. See Table 64. UART Line Status Registers(UART0_LSR = 00C5h, UART1_LSR = 00 D5h) Bit Reset CPU Access Note Read only. Bit ...

Page 128

Bit Position UART Modem Status Register This register is used to show the status of the UART signals. See PS015313-0508 Value Description 0 No framing error detected for character at the top ...

Page 129

Table 65. UART Modem Status Registers(UART0_MSR = 00C6h, UART1_MSR = 00 D6h) Bit Reset CPU Access Note Read only. Bit Position 7 DCD DSR 4 CTS 3 DDCD 2 TERI 1 DDSR 0 DCTS PS015313-0508 ...

Page 130

UART Scratch Pad Register The UARTx_SPR register can be used by the system as a general-purpose Read/Write reg- ister. See Table 66. Table 66. UART Scratch Pad Registers(UART0_SPR = 00C7h, UART1_SPR = 00D7h) Bit Reset CPU Access Note: R/W = ...

Page 131

Infrared Encoder/Decoder The eZ80F92 device contains a UART to infrared encoder/decoder (endec). The IrDA endec is integrated with the on-chip UART0 to allow easy communication between the CPU and IrDA Physical Layer Specification Version 1.4-compatible infrared transceivers, as displayed in ...

Page 132

See Universal Asynchronous Receiver/Transmitter on page 104 for more informa- tion about the UART and its Baud Rate Generator. Transmit The data to be transmitted via the IR transceiver is first sent to UART0. The UART trans- mit signal ...

Page 133

The UART baud rate clock is used by the IrDA endec to generate the demodulated signal (RxD) that drives the UART. Each UART bit period is sixteen baud-clocks wide. Each IR_RXD bit is encoded during a bit period such that ...

Page 134

Table 67. IrDA Physical Layer 1.4 Pulse Durations Specifications (Continued) Baud Rate 57600 115200 Receiver Frequency Divider The IrDA receiver uses a 6-bit frequency divider. The value is derived from the system clock to measure IR_RxD pulses. The IrDA endec ...

Page 135

Setting the upper 4 bits of IR_CTL to receiver. In this mode, the IrDA receiver uses edge detection on the IR_RxD bit stream. Jitter Due to the inherent sampling of the received IR_RxD signal by the BIt Rate Clock, some ...

Page 136

Infrared Encoder/Decoder Register After a RESET, the Infrared Encoder/Decoder register is set to its default value. Any writes to unused register bits are ignored and reads return a value of 0. The IR_CTL regis- ter is listed in Table Table ...

Page 137

Serial Peripheral Interface The Serial Peripheral Interface (SPI synchronous interface allowing several SPI-type devices to be interconnected. The SPI is a full-duplex, synchronous, character-oriented communication channel that employs a four-wire interface. The SPI block consists of a transmitter, ...

Page 138

SS ENABLE MOSI DATAIN CLKIN SCK SPI Signals The four basic SPI signals are: 1. MISO (Master In, Slave Out) 2. MOSI (Master Out, Slave In) 3. SCK (SPI Serial Clock (Slave Select) These SPI signals are discussed ...

Page 139

When the Clock Phase bit (CPHA) is set to 0, the shift clock is the logical with SCK. In this clock phase mode, SS must go High between successive characters in an SPI message. When CPHA is ...

Page 140

Table 71. SPI Clock Phase and Clock Polarity Operation CPHA CPOL SPI Functional Description When a master transmits to a slave device via the MOSI signal, the slave device responds by sending data to the master ...

Page 141

SPI Flags Mode Fault The Mode Fault flag (MODF) indicates that there may be a multimaster conflict for sys- tem control. The MODF bit is normally cleared to 0 and is only set to 1 when the master device’s SS ...

Page 142

Upon RESET, the 16-bit BRG divisor value resets to a Master, the BRG divisor value must be set to a value of is operating as a Slave, the BRG divisor value must be set to a value of A software ...

Page 143

A Write to either the Low or High byte registers for the BRG Divisor Latch causes both bytes to be loaded into the BRG counter and the count restarted. See 73. Table 72. SPI Baud Rate Generator Register—Low Byte(SPI_BRG_L = ...

Page 144

Table 74. SPI Control Register(SPI_CTL = 00BAh) Bit Reset CPU Access Note Read Only; R/W = Read/Write. Bit Position 7 IRQ_EN 6 5 SPI_EN 4 MASTER_EN 3 CPOL 2 CPHA [1:0] SPI Status Register The SPI Status Read ...

Page 145

Bit Position 7 SPIF 6 WCOL 5 4 MODF [3:0] PS015313-0508 Value Description 0 SPI data transfer is not finished. 1 SPI data transfer is finished. If enabled, an interrupt is generated. This bit flag is cleared ...

Page 146

SPI Transmit Shift Register The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data onto the SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly into the shift ...

Page 147

Bit Position [7:0] RX_DATA PS015313-0508 Value Description 00h–FFh SPI received data. eZ80F92/eZ80F93 Product Specification 140 Serial Peripheral Interface ...

Page 148

I2C Serial I/O Interface General Characteristics 2 The I C serial I/O bus is a two-wire communication interface that can operate in four modes: 1. MASTER TRANSMIT 2. MASTER RECEIVE 3. SLAVE TRANSMIT 4. SLAVE RECEIVE 2 ...

Page 149

Data Validity The data on the SDA line must be stable during the High period of the clock. The High or Low state of the data line can only change when the clock signal on the SCL line is Low ...

Page 150

Transferring Data Byte Format Every character transferred on the SDA line must be a single 8-bit byte. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an Acknowledge (ACK) Figure 34. ...

Page 151

The slave-transmitter must release the data line to allow the master to generate a STOP or a repeated START condition. Data Output by Transmitter Data Output by Receiver SCL Signal from Master START Condition Clock Synchronization All masters generate their ...

Page 152

CLK1 Signal CLK2 Signal SCL Signal Arbitration A master may start a transfer only if the bus is free. Two or more masters may generate a START condition within the minimum hold time of the START condition which results in ...

Page 153

In other words, arbitration is not allowed between: • A repeated START condition and a data bit • A STOP condition and a data bit • A repeated START condition and a STOP condition Clock Synchronization for Handshake The Clock ...

Page 154

Table 78 Master Transmit Status Codes 2 Code I C State 18h Addr+W transmitted, ACK received 20h Addr+W transmitted, ACK not received 38h Arbitration lost 68h Arbitration lost, +W received, ACK transmitted 78h Arbitration lost, General call ...

Page 155

Table 79 10-Bit Master Transmit Status Codes 2 Code I C State 38h Arbitration lost 68h Arbitration lost, SLA+W received, ACK transmitted B0h Arbitration lost, SLA+R received, ACK transmitted D0h Second Address byte + W transmitted, ACK ...

Page 156

Table 80 Master Transmit Status Codes For Data Bytes (Continued) 2 Code I C State Data byte transmitted, 30h ACK not received Arbitration lost 38h When all bytes are transmitted, the microcontroller should write ...

Page 157

Table 81 Master Receive Status Codes (Continued) 2 Code I C State 48h Addr + R transmitted, ACK not received 38h Arbitration lost 68h Arbitration lost, SLA+W received, ACK transmitted 78h Arbitration lost, General call addr received, ...

Page 158

Table 82 Master Receive Status Codes For Data Bytes 2 Code I C State Data byte received, 50h ACK transmitted Data byte received, 58h NACK transmitted Arbitration lost in 38h NACK bit When all bytes are received, ...

Page 159

IFLG is set and the I2C_SR register contains the idle state. The AAK bit must be set to 1 before reentering SLAVE mode acknowledge is received after transmitting a byte, the IFLG is set and ...

Page 160

I C Registers Addressing The processor interface provides access to six 8-bit registers: four Read/Write registers, one Read Only register and two Write Only registers, as listed in 2 Table 83 Register Descriptions Register I2C_SAR I2C_XSAR I2C_DR ...

Page 161

Table 84 Slave Address Registers(I2C_SAR = 00C8h) Bit Reset CPU Access Note: R/W = Read/Write. Bit Position [7:1] SLA 0 GCE Extended Slave Address Register The I2C_XSAR register is used in conjunction with the ...

Page 162

Table 85 Extended Slave Address Registers(I2C_XSAR = 00C9h) Bit Reset CPU Access Note: R/W = Read/Write. Bit Position [7:0] SLAX Data Register This register contains the data byte/slave address to be transmitted or the ...

Page 163

I C responds to calls to its slave address and to the general call address if the GCE bit (I2C_SAR[0]) is set to 1. When the Master Mode Start bit (STA) is set to 1, ...

Page 164

Table 87 Control Registers(I2C_CTL = 00CBh) Bit Reset CPU Access Note: R/W = Read/Write Read Only. Bit Position 7 IEN 6 ENAB 5 STA 4 STP 3 IFLG 2 AAK [1:0] PS015313-0508 ...

Page 165

I C Status Register The I2C_SR register is a Read Only register that contains a 5-bit status code in the five msbs: the three lsbs are always 0. The Read Only I2C_SR registers share the same I/O addresses as ...

Page 166

Table 89 Status Codes (Continued) Code Status Address and Read bit transmitted, ACK received 40h Address and Read bit transmitted, ACK not received 48h Data byte received in MASTER mode, ACK transmitted 50h Data byte received in ...

Page 167

I C Clock Control Register The I2C_CCR register is a Write Only register. The seven LSBs control the frequency at 2 which the I C bus is sampled and the frequency of the MASTER mode. The ...

Page 168

Bus Clock Speed 2 The I C bus is defined for bus clock speeds up to 100 kbps (400 kbps in FAST mode). To ensure correct detection of START and STOP conditions on the bus, the I 2 ple the ...

Page 169

... Zilog Debug Interface Introduction The Zilog Debug Interface (ZDI) provides a built-in debugging interface to the eZ80 CPU. ZDI provides basic in-circuit emulation features including: • Examining and modifying internal registers • Examining and modifying memory • Starting and stopping the user program • ...

Page 170

... TCK (ZCL) MCU TDI (ZDA) Figure 38.Schematic For Building a Target Board USB Smart Cable Connector PS015313-0508 ZDI Clock Frequency 1 MHz 2 MHz 4 MHz 8 MHz 10 K‰ 10 K‰ 6-Pin Target Connector eZ80F92/eZ80F93 Product Specification TV DD (Target Zilog Debug Interface 163 ...

Page 171

... ZCL signal High. ZCL ZDA Start Signal PS015313-0508 Figure 39 Figure 40 on page 165. When an operation is completed, the master ZDI Data In ZDI Data In (Write) (Write) Figure 39.ZDI Write Timing eZ80F92/eZ80F93 Product Specification and Figure 40 on page 165 dis- Zilog Debug Interface 164 ...

Page 172

... START command is issued at completion of the Read or Write operation, the operation PS015313-0508 ZDI Data Out (Read) Figure 40.ZDI Read Timing ® returns the eZ80 Product ID Low Byte while a Write to this same eZ80F92/eZ80F93 Product Specification ZDI Data Out (Read) Zilog Debug Interface 165 ...

Page 173

... Figure 41.ZDI Address Write Timing displays the timing for ZDI single-byte Write operations. ZDI Data Byte msb of DATA eZ80F92/eZ80F93 Product Specification Single-Bit Byte Separator or new ZDI START Signal R/W 0/1 lsb 0 = WRITE 1 = READ lsb of DATA End of Data or New ZDI START Signal Zilog Debug Interface 166 ...

Page 174

... The msb is shifted out first. byte Read operations. PS015313-0508 Figure 43 ZDI Data Bytes msb lsb of DATA of DATA Byte 1 Byte 1 Byte Separator Figure 44 eZ80F92/eZ80F93 Product Specification displays the timing for ZDI Block 0 msb of DATA Byte 2 Single-Bit displays the timing for ZDI single- Zilog Debug Interface 167 ...

Page 175

... Figure 45 displays the ZDI’s Block Read timing. ZDI Data Bytes msb lsb of DATA of DATA Byte 1 Byte 1 Byte Separator eZ80F92/eZ80F93 Product Specification lsb of DATA End of Data or New ZDI START Signal ), the address 20h 0 msb of DATA Byte 2 Single-Bit Zilog Debug Interface 168 ...

Page 176

... To prevent data errors, ZDI should avoid data transmission while another device is con- trolling the bus. Finally, exiting ZDI DEBUG mode while an external peripheral controls the address and data buses, as indicated by BUSACK assertion, may produce unpredictable results. PS015313-0508 eZ80F92/eZ80F93 Product Specification 169 Zilog Debug Interface ...

Page 177

... Write Data Low Byte Write Data High Byte Write Data Upper Byte Read/Write Control register Bus Control register Instruction Store 4 Instruction Store 3 Instruction Store 2 Instruction Store 1 Instruction Store 0 Write Memory register Zilog Debug Interface 170 Reset Value XXh XXh XXh XXh XXh XXh XXh ...

Page 178

... Read Memory Address High Byte register Read Memory Address Upper Byte register Bus Status register Read Memory Data Value ® mode, the address is supplied by on page 172. eZ80F92/eZ80F93 Product Specification 171 Reset Value 07h 00h XXh 00h XXh XXh XXh 00h XXh Zilog Debug Interface ...

Page 179

... Value Description 00h– The four sets of ZDI address match registers are used for FFh setting the addresses for generating BREAK points. The 24-bit addresses are supplied by {ZDI_ADDRx_U, ZDI_ADDRx_H, ZDI_ADDRx_L, where Table 96 on page 173. eZ80F92/eZ80F93 Product Specification Zilog Debug Interface 172 ...

Page 180

... The ZDI BREAK, upon matching BREAK address 1, is disabled. 1 The ZDI BREAK, upon matching BREAK address 1, is enabled. 0 The ZDI BREAK, upon matching BREAK address 0, is disabled. 1 The ZDI BREAK, upon matching BREAK address 0, is enabled. eZ80F92/eZ80F93 Product Specification Zilog Debug Interface 173 ...

Page 181

... BREAK when only the upper 2 bytes of the 24-bit address, ADDR[23:8], match the 2 bytes value {ZDI_ADDR0_U, ZDI_ADDR0_H result, a BREAK can occur anywhere within a 256-byte page. 0 ZDI SINGLE STEP mode is disabled. 1 ZDI SINGLE STEP mode is enabled. ZDI asserts a BREAK following execution of each instruction. eZ80F92/eZ80F93 Product Specification 174 Zilog Debug Interface ...

Page 182

... Write Address Spaces) Bit Reset CPU Access Note Write Only. Bit Position 7 ZDI_RESET [6:0] PS015313-0508 97 Value Description 0 No action. 1 Initiate a RESET of the CPU. This bit is automatically cleared at the end of the RESET event. 0000000 Reserved. eZ80F92/eZ80F93 Product Specification Zilog Debug Interface 175 ...

Page 183

... ZDI_RW_CTL register. The 24-bit data value is stored as {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. If less than 24 bits of data are required to complete the required operation, the data is taken from the LSBs. Table 99 Table 99 eZ80F92/eZ80F93 Product Specification 16h page 177. When a Read oper- ® on page 177. Refer to the eZ80 Zilog Debug Interface 176 ...

Page 184

... ZDI_WR_U ← IXH ZDI_WR_H ← IXL ZDI_WR_L Write IY ← IYU ZDI_WR_U ← IYH ZDI_WR_H ← IYL ZDI_WR_L Write SP In ADL mode SPL In Z80 mode SPS Write PC ← PC[23:16] ZDI_WR_U ← PC[15:8] ZDI_WR_H ← PC[7:0] ZDI_WR_L Reserved Reserved Zilog Debug Interface 177 ...

Page 185

... The ZDI programmer must execute the exchange instruction (EXX) to gain access to the alternate eZ80 CPU register set. PS015313-0508 Hex Value 8A ← AF’ ← BC’ ← DE’ ← HL’ 8B eZ80F92/eZ80F93 Product Specification Command Reserved Write memory from current PC value, increment PC Zilog Debug Interface 178 ...

Page 186

... Deassert the bus acknowledge pin (BUSACK) to return control of the address and data buses back to ZDI. 1 Assert the bus acknowledge pin (BUSACK) to pass control of the address and data buses to an external peripheral. 000000 Reserved. eZ80F92/eZ80F93 Product Specification 179 Zilog Debug Interface ...

Page 187

... These registers contain the Op Codes and operands for FFh immediate execution by the CPU following a Write to ZDI_IS0. The ZDI_IS0 register contains the first Op Code of the instruction. The remaining ZDI_ISx registers contain any additional Op Codes or operand dates required for execution of the required instruction. eZ80F92/eZ80F93 Product Specification Zilog Debug Interface 180 ...

Page 188

... Write to this address is written to the address indicated by the current program counter. The program counter is incremented following each 8 bits of data. In Z80 MEMORY mode, ({MBASE, PC[15:0]}) transferred data. In ADL MEMORY mode, ← (PC[23:0]) 8 bits of transferred data. eZ80F92/eZ80F93 Product Specification Table 102 ← 8 bits of Zilog Debug Interface 181 ...

Page 189

... Note Read Only. Bit Position [7:0] ZDI_ID_H PS015313-0508 104 Value Description 07h {ZDI_ID_H, ZDI_ID_L} = {00h, 07h} indicates the eZ80F92 product Value Description 00h {ZDI_ID_H, ZDI_ID_L} = {00h, 07h} indicates the eZ80F92 product. eZ80F92/eZ80F93 Product Specification ® product being addressed. See Zilog Debug Interface 182 ...

Page 190

... Identifies the current revision of the eZ80F92 product. FFh Value Description 0 The CPU is not functioning in ZDI mode. 1 The CPU is currently functioning in ZDI mode. 0 Reserved. 0 The CPU is not currently in HALT or SLEEP mode. 1 The CPU is currently in HALT or SLEEP mode. eZ80F92/eZ80F93 Product Specification Zilog Debug Interface 183 ...

Page 191

... R R Value Description 00h– Values read from the memory location as requested by the FFh ZDI Read Control register during a ZDI Read operation. The 24-bit value is supplied by {ZDI_RD_U, ZDI_RD_H, ZDI_RD_L}. eZ80F92/eZ80F93 Product Specification ® MEMORY mode. Table 107 Zilog Debug Interface 184 ...

Page 192

... Address and data buses are relinquished to an external peripheral. bus acknowledge is asserted (BUSACK pin is Low). 000000 Reserved. ® MEMORY mode, the memory ® CPU User Manual (UM0077) for more information regard- Table 109 eZ80F92/eZ80F93 Product Specification 185 page 186. Zilog Debug Interface ...

Page 193

... FFh CPU’s program counter. In Z80 data is transferred out from address {MBASE, PC[15:0]}. In ADL Memory mode, 8-bit data is transferred out from address PC[23:0]. eZ80F92/eZ80F93 Product Specification 186 ® MEMORY mode, 8-bit Zilog Debug Interface ...

Page 194

... The OCI provides run control, memory and register visibility, complex break- points, and trace history features. The OCI employs all of the functions of the ZDI as described in the Zilog Debug Interface section that starts on page 162. It also adds the following debug features: • ...

Page 195

... See the Zilog Debug Interface sec- tion on page 162 for more information about ZDI. OCI Interface There are five dedicated pins on the eZ80F92 device for the OCI interface. Four pins—TCK, TMS, TDI, and TDO—are required for IEEE Standard 1149.1-compli- ant JTAG ports ...

Page 196

OCI Information Requests For additional information regarding On-Chip Instrumentation order OCI debug tools, contact: First Silicon Solutions, Inc. 5440 SW Westgate Drive, Suite 240 Portland, OR 97221 Phone: (503) 292-6730 Fax: (503) 292-5840 www.fs2.com PS015313-0508 eZ80F92/eZ80F93 Product Specification ...

Page 197

Random Access Memory The eZ80F92 features 8 KB (8192 bytes) single-port data Random Access Memory (RAM) for general-purpose use. The eZ80F93 features 4 KB (4096 bytes) general-pur- pose RAM. RAM can be enabled or disabled, and it can be relocated ...

Page 198

Memory Location FFFFFFh 7AFFFFh General Purpose 7AF000h 000000h Figure 47.eZ80F93 On-Chip RAM Memory Addressing Example When enabled, on-chip RAM assumes priority over on-chip Flash Memory and any Mem- ory Chip Selects that can also be enabled in the same address ...

Page 199

RAM Control Registers RAM Control Register The internal data RAM can be disabled by clearing the RAM_EN bit. The default, upon RESET, is for RAM to be enabled. Table 111. RAM Control Register; (RAM_CTL = 00B4h) Bit Reset CPU Access ...

Page 200

Flash Memory Flash Memory Arrangement in eZ80F92 The eZ80F92 device features 128 KB (131,072 bytes) of non-volatile Flash memory with Read/Write/Erase capability. The main Flash memory array is arranged in 128 pages with eight rows per page and 128 bytes ...

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