EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet

IC ACCLAIM MCU 128KB 100LQFP

EZ80F92AZ020EG

Manufacturer Part Number
EZ80F92AZ020EG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F92AZ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-3871
EZ80F92AZ020EG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F92AZ020EG
Manufacturer:
Zilog
Quantity:
10 000
Issues Related to eZ80F92 and eZ80F93 Microcontrollers
The errata listed in
eZ80F93 microcontrollers.
Table 1. Errata to eZ80F92 and eZ80F93 Devices
No
1
2
3
Issue
The infrared encoder/
decoder (endec) receiver
misses bits when
configured for low-data
rates and the incoming
signals are only 1.6 µs.
The real time clock (RTC)
consumes excess current
when the eZ80F92 and
eZ80F93 MCUs are not in
SLEEP mode.
Reading from Flash
memory during ERASE or
ROW PROGRAM
operations.
Table 1
highlights the issues and workarounds (if available) related to eZ80F92 and
Copyright ©2010 by ZiLOG, Inc. All rights reserved.
UP004909-0910
Detailed Description
The infrared endec samples the incoming IR pulses, using the baud rate
clock divided by 16. This sampling rate is not sufficient to capture the
incoming pulses when they use a short-pulse format and low-data rates.
This short pulse, 1.6 µs, is within IrDA specifications; however, not all
transmitters use this particular signalling format. When the external
transmitter is sending
eZ80F93 devices receive the data properly.
When the eZ80F92 and eZ80F93 devices are not in SLEEP mode, the
system clock drives the RTC's control and data registers. As a result,
excess current is consumed through the RTC_V
power to the certain portion of the clock tree that drives the RTC
registers. This current consumption is a function of operating frequency.
Typical current consumption is 500 µA at 20 MHz.
The on-chip Flash memory controller automatically obstructs Flash
memory Reads issued during ERASE and ROW PROGRAM operations
only when configured for one or more Wait states. When the Flash
memory controller is set for zero wait states, such Reads can return
incorrect data and can cause corruption to the contents of Flash
memory.
Workarounds
1. Execution of row programming from Flash memory is not supported.
2. If executing a Flash ERASE from RAM or external memory, the user
However, before executing a Flash ERASE or ROW PROGRAM,
configure Flash for one or more wait states. After the ERASE or ROW
PROGRAM operation is completed, Flash memory can again be
configured for zero wait states.
code should monitor either the PG_ERASE/MASS_ERASE flags in
the FLASH_PGCTL register or the DONE flag in the FLASH_IRQ
register. The user code waits for the ERASE or ROW PROGRAM
operation to complete before proceeding.
www.zilog.com
Product Update
Errata for eZ80F92 and eZ80F93
MCUs
3
/
16
IR pulses, the endec on the eZ80F92 and
DD
pin that supplies

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EZ80F92AZ020EG Summary of contents

Page 1

... Flash memory. Workarounds 1. Execution of row programming from Flash memory is not supported executing a Flash ERASE from RAM or external memory, the user Copyright ©2010 by ZiLOG, Inc. All rights reserved. Product Update Errata for eZ80F92 and eZ80F93 MCUs 3 ...

Page 2

Table 1. Errata to eZ80F92 and eZ80F93 Devices (Continued) No Issue Detailed Description 4 A pulse on the SCL line A pulse on the SCL line prior to a START condition or after a STOP 2 when the I C ...

Page 3

Table 1. Errata to eZ80F92 and eZ80F93 Devices (Continued) No Issue Detailed Description 6 GPIO edge-trigger For edge triggered interrupts (Mode 6 and Mode 9), erroneous logic interrupt mapping error dependencies for the interrupt clearing logic exist on all port ...

Page 4

Table 1. Errata to eZ80F92 and eZ80F93 Devices (Continued) No Issue Detailed Description (continued from previous page) PB3 Input, falling or rising edge interrupt, depending on hardware PB4 Input (not used) PB5 Input, falling edge interrupt PB6 Input, dual edge ...

Page 5

Table 1. Errata to eZ80F92 and eZ80F93 Devices (Continued) No Issue Detailed Description 7 The UART is continually The root cause of this issue has been duplicated with certain signal interrupting; the user conditions after which a software instruction was ...

Page 6

Table 1. Errata to eZ80F92 and eZ80F93 Devices (Continued) No Issue Detailed Description (continued Ignore any data trapped in the Rx fifo */ while( Lsr & LSR_DR ) { Lsr = BSP_RD32( pUart->Base | UART_REG_RBR ); Lsr = ...

Page 7

... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, eZ80Acclaim! and ZNEO are trademarks or registered trademarks of ZiLOG, Inc. All other product or service names are the property of their respective owners. UP004909-0910 ...

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