EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 117

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Note:
BRG Control Registers
Recommended Usage of the Baud Rate Generator
The following is the normal sequence of operations that should occur after the eZ80F92
device is powered on to configure the Baud Rate Generator:
•
•
•
•
UART Baud Rate Generator Register—Low and High Bytes
The registers hold the Low and High bytes of the 16-bit divisor count loaded by the pro-
cessor for UART baud rate generation. The 16-bit clock divisor value is returned by
{UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two available
UART devices. Upon RESET, the 16-bit BRG divisor value resets to
16-bit divisor value must be between
are invalid, and proper operation is not guaranteed. As a result, the minimum BRG clock
divisor ratio is 2.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter. The count is then restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to
access this register. See
Register (UARTx_LCTL) on page 116 for more information.
Table 52. UART Baud Rate Generator Register—Low Bytes(UART0_BRG_L =
00C0h, UART1_BRG_L = 00D0h)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Assert and deassert RESET
Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers
Program the UARTx_BRG_L and UARTx_BRG_H registers
Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers
The UARTx_BRG_L registers share the same address space with the UARTx_RBR
and UARTx_THR registers. The UARTx_BRG_H registers share the same address
space with the UARTx_IER registers. Bit 7 of the associated UART Line Control
register (UARTx_LCTL) must be set to 1 to enable access to the BRG registers.
Table 52
R/W
7
0
and
R/W
6
0
0002h
Table 53
R/W
5
0
and
on page 111. See the UART Line Control
Universal Asynchronous Receiver/Transmitter
FFFFh
R/W
4
0
as the values
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
0002h
0000h
R/W
. The initial
1
1
and
0001h
R/W
0
0
110