EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 123

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
UART Line Control Register
This register is used to control the communication control parameters.
See
Table 60. UART Line Control Registers(UART0_LCTL = 00C3h, UART1_LCTL =
00D3h)
Bit
Position
1
CLRRXF
0
FIFOEN
Note: *Receive FIFO is not enabled during
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
DLAB
Note: *Receive Parity is set to SPACE in MULTIDROP mode.
Table 60
and
Value
0
1
0
1
Value
0
1
Table 61
Description
No effect.
Clear the receive FIFO, clear the receive error FIFO, and reset
the receive FIFO pointer. Valid only if the FIFO is enabled.
Transmit and receive FIFOs are disabled. Transmit and receive
buffers are only 1 byte deep.
Transmit and receive FIFOs are enabled*.
R/W
Description
Access to the UART registers at I/O addresses UARTx_RBR,
UARTx_THR, and UARTx_IER is enabled.
Access to the Baud Rate Generator registers at I/O addresses
UARTx_BRG_L and UARTx_BRG_H is enabled.
on page 118.
7
0
R/W
6
0
MULTIDROP
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
mode.
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
116