EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 124

IC ACCLAIM MCU 128KB 100LQFP

EZ80F92AZ020EG

Manufacturer Part Number
EZ80F92AZ020EG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F92AZ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-3871
EZ80F92AZ020EG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F92AZ020EG
Manufacturer:
Zilog
Quantity:
10 000
PS015313-0508
Bit
Position
6
SB
5
FPE
4
EPS
3
PEN
[2:0]
CHAR
Note: *Receive Parity is set to SPACE in MULTIDROP mode.
Value
0
1
0
1
0
1
0
1
000–
111
Description
Do not send a BREAK signal.
Send Break
UART sends continuous zeroes on the transmit output from the
next bit boundary. The transmit data in the transmit shift
register is ignored. After forcing this bit High, the
0 only after the bit boundary is reached. Just before forcing
T
the transmit FIFO during a break should be written only after
the THRE bit of UARTx_LSR register goes High. This new data
is transmitted after the UART recovers from the break. After the
break is removed, the UART recovers from the break for the
next BRG edge.
Do not force a parity error.
Force a parity error. When this bit and the party enable bit
(PEN) are both 1, an incorrect parity bit is transmitted with the
data byte.
Use odd parity for transmit and receive. The total number of 1
bits in the transmit data plus parity bit is odd. Use as a SPACE
bit in MULTIDROP mode. See
select definitions.*
Use even parity for transmit and receive. The total number of 1
bits in the transmit data plus parity bit is even. Use as a MARK
bit in MULTIDROP mode. See
select definitions.
Parity bit transmit and receive is disabled.
Parity bit transmit and receive is enabled. For transmit, a parity
bit is generated and transmitted with every data character. For
receive, the parity is checked for every incoming data
character. In MULTIDROP mode, receive parity is checked for
space parity.
UART Character Parameter Selection—see
118 for a description of the values.
x
D
to 0, the transmit FIFO is cleared. Any new data written to
Universal Asynchronous Receiver/Transmitter
Table 62
Table 62
Product Specification
on page 118 for parity
on page 118 for parity
eZ80F92/eZ80F93
Table 61
T
x
D
on page
output is
117

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