EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 142

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Data Transfer Procedure with SPI Configured as the Master
Data Transfer Procedure with SPI Configured as a Slave
SPI Registers
Upon RESET, the 16-bit BRG divisor value resets to
a Master, the BRG divisor value must be set to a value of
is operating as a Slave, the BRG divisor value must be set to a value of
A software Write to either the Low- or High-byte registers for the BRG Divisor Latch
causes both the Low and High bytes to load into the BRG counter, and causes the count to
restart.
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. External device must deassert the SS pin if currently asserted.
3. Load the SPI Control Register, SPI_CTL.
4. Assert the ENABLE pin of the slave device using a GPIO pin.
5. Load the SPI Transmit Shift Register, SPI_TSR.
6. When the SPI data transfer is complete, deassert the ENABLE pin of the slave device.
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while the SPI
3. Wait for the external SPI Master device to initiate the data transfer by asserting SS.
There are six registers in the Serial Peripheral Interface which provide control, status, and
data storage functions. The SPI registers are described in the following paragraphs.
SPI Baud Rate Generator Registers—Low Byte and High Byte
These registers hold the Low and High bytes of the 16 bit divisor count loaded by the pro-
cessor for baud rate generation. The 16 bit clock divisor value is returned by
{SPI_BRG_H, SPI_BRG_L}. Upon RESET, the 16 bit BRG divisor value resets to
0002h
FFFFh
0004h
slave is currently receiving data.
. When configured as a Master, the 16 bit divisor value must be between
, inclusive. When configured as a Slave, the 16 bit divisor value must be between
and
FFFFh
, inclusive.
0002h
0003h
. When the SPI is operating as
Product Specification
or greater. When the SPI
Serial Peripheral Interface
eZ80F92/eZ80F93
0004h
0003h
or greater.
and
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