EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 143

IC ACCLAIM MCU 128KB 100LQFP

EZ80F92AZ020EG

Manufacturer Part Number
EZ80F92AZ020EG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F92AZ020EG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
269-3871
EZ80F92AZ020EG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F92AZ020EG
Manufacturer:
Zilog
Quantity:
10 000
PS015313-0508
A Write to either the Low or High byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter and the count restarted. See
73.
Table 72. SPI Baud Rate Generator Register—Low Byte(SPI_BRG_L = 00B8h)
sterister is used to control and setup the serial peripheral interface. The SPI should be dis-
Table 73. SPI Baud Rate Generator Register—High Byte (SPI_BRG_H = 00B9h)
This register is used to control and setup the serial peripheral interface. The SPI should be
disabled prior to making any changes to CPHA or CPOL. See disabled prior to making
any changes to CPHA or CPOL. See
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPI_BRG_L
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPI_BRG_H
Value
00h–
FFh
Value
00h–
FFh
R/W
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
R/W
Description
These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
7
0
7
0
R/W
R/W
6
0
6
0
Table 74
R/W
R/W
5
0
5
0
on page 137.
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
Product Specification
Serial Peripheral Interface
R/W
R/W
Table 72
2
0
2
0
eZ80F92/eZ80F93
R/W
R/W
1
1
1
0
and
Table
R/W
R/W
0
0
0
0
136

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