EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 146

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
SPI Transmit Shift Register
The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data onto
the SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly
into the shift register for transmission. A Write to this register within an SPI device config-
ured as a master initiates transmission of the byte of the data loaded into the register. At
the completion of transmitting a byte of data, the SPIF status bit (SPI_SR[7]) is set to 1 in
both the master and slave devices.
The SPI Transmit Shift Write Only register shares the same address space as the SPI
Receive Buffer Read Only register. See
Table 76. SPI Transmit Shift Register(SPI_TSR = 00BCh)
SPI Receive Buffer Register
The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive data from
the serial bus. The SPIF bit must be cleared prior to a second transfer of data from the shift
register or an overrun condition exists. In cases of overrun the byte that caused the overrun
is lost.
The SPI Receive Buffer Read Only register shares the same address space as the SPI
Transmit Shift Write Only register. See
Table 77. SPI Receive Buffer Register(SPI_RBR = 00BCh)
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:0]
TX_DATA
Bit
Reset
CPU Access
Note: R = Read Only.
Value Description
00h–
FFh
W
SPI transmit data.
X
X
R
7
7
W
X
X
R
6
6
Table
Table
W
R
X
X
5
5
77.
76.
W
R
X
X
4
4
W
R
X
X
3
3
Product Specification
Serial Peripheral Interface
W
R
X
X
2
2
eZ80F92/eZ80F93
W
X
X
R
1
1
W
X
X
R
0
0
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