EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 149

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Data Validity
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line can only change when the clock signal on the SCL line is Low as
displayed in
START and STOP Conditions
Within the I
STOP conditions. See
High indicates a START condition. A Low-to-High transition on the SDA line while SCL
is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after the START condition. The bus is considered to be free a defined time after
the STOP condition.
SDA Signal
SDA Signal
SCL Signal
SCL Signal
2
Figure
C bus protocol, unique situations arise which are defined as START and
START Condition
Figure 33. START and STOP Conditions In I
S
32.
Data Valid
Data Line
Figure 32. I
Stable
Figure
33. A High-to-Low transition on the SDA line while SCL is
Data Allowed
2
Change of
C Clock and Data Relationship
2
C Protocol
Product Specification
STOP Condition
I2C Serial I/O Interface
P
142