EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 152

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Arbitration
A master may start a transfer only if the bus is free. Two or more masters may generate a
START condition within the minimum hold time of the START condition which results in
a defined START condition to the bus. Arbitration takes place on the SDA line, while the
SCL line is at the High level, in such a way that the master which transmits a High level,
while another master is transmitting a Low level switches off its data output stage because
the level on the bus does not correspond to its own level.
Arbitration can continue for many bits. Its first stage is comparison of the address bits. If
the masters are each trying to address the same device, arbitration continues with compar-
ison of the data. Because address and data information about the I
tration, no information is lost during this process. A master which loses the arbitration can
generate clock pulses until the end of the byte in which it loses the arbitration.
If a master also incorporates a slave function and it loses arbitration during the addressing
stage, it's possible that the winning master is trying to address it. The losing master must
switch over immediately to its slave-receiver mode.
cedure for two masters. Of course, more may be involved (depending on how many mas-
ters are connected to the bus). The moment there is a difference between the internal data
level of the master generating DATA 1 and the actual level on the SDA line, its data output
is switched off, which means that a High output level is then connected to the bus. As a
result, the data transfer initiated by the winning master is not affected. Because control of
the I
no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still
in progress at the moment when a repeated START condition or a STOP condition is trans-
mitted to the I
must send this repeated START condition or STOP condition at the same position in the
format frame.
CLK1 Signal
CLK2 Signal
SCL Signal
2
C bus is decided solely on the address and data sent by competing masters, there is
2
C bus. If it is possible for such a situation to occur, the masters involved
Figure 36.Clock Synchronization In I
State
Wait
Counter
Reset
Start Counting
High Period
Figure 36
2
C Protocol
displays the arbitration pro-
Product Specification
2
C bus is used for arbi-
I2C Serial I/O Interface
145