EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 155

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Table 79. I
If a repeated START condition is transmitted, the status code is
After each data byte is transmitted, the IFLG is 1 and one of the status codes listed in
Table 80
Table 80. I
Code
38h
68h
B0h
D0h
D8h
Code I
28h
Data byte transmitted,
ACK received
2
I
Arbitration lost
Arbitration lost,
SLA+W received,
ACK transmitted
Arbitration lost,
SLA+R received,
ACK transmitted
Second Address byte
+ W transmitted,
ACK received
Second Address byte
+ W transmitted,
ACK not received
is in the I2C_SR register.
2
C State
C State
2
2
C 10-Bit Master Transmit Status Codes
C Master Transmit Status Codes For Data Bytes
Microcontroller Response Next I
Write byte to DATA,
clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
Microcontroller Response
Clear IFLG
Or set STA, clear IFLG
Clear IFLG, clear AAK = 0
Or clear IFLG, set AAK = 1
Write byte to DATA,
clear IFLG, clear AAK = 0
Or write byte to DATA,
clear IFLG, set AAK = 1
Write byte to DATA,
clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
Same as code D0h
Transmit data byte,
receive ACK
Transmit repeated START
Transmit STOP
Transmit START then STOP
10h
Next I
Return to idle
Transmit START when
bus free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit last byte,
receive ACK
Transmit data byte,
receive ACK
Transmit data byte,
receive ACK
Transmit repeated
START
Transmit STOP
Transmit STOP then
START
Same as code D0h
Product Specification
2
C Action
instead of
I2C Serial I/O Interface
2
C Action
08h
.
148