EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 156

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Table 80. I
When all bytes are transmitted, the microcontroller should write a 1 to the STP bit in the
I2C_CTL register. The I
to the idle state.
Master Receive
In MASTER RECEIVE mode, the I
ter.
After the START condition is transmitted, the IFLG bit is 1 and the status code
loaded in the I2C_SR register. The I2C_DR register should be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit should be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in
I2C_SR register.
Table 81. I
Code I
30h
38h
Code
40h
R = Read bit; that is, the lsb is set to 1.
Data byte transmitted,
ACK not received
Arbitration lost
2
C State
2
2
I
Addr + R
transmitted, ACK
received
C Master Transmit Status Codes For Data Bytes (Continued)
C Master Receive Status Codes
2
C State
2
C then transmits a STOP condition, clears the STP bit and returns
Microcontroller Response Next I
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
Microcontroller Response Next I
For a 7-bit address,
clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
For a 10-bit address
Write extended address
byte to DATA, clear IFLG
2
C receives a number of bytes from a slave transmit-
Same as code 28h
Return to idle
Transmit START when bus
free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit extended
address byte
Product Specification
2
Table 81
C Action
I2C Serial I/O Interface
2
C Action
is in the
08h
is
149