EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 18

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Table 1. 100-Pin LQFP Pin Identification of the eZ80F92 Device (Continued)
PS015313-0508
Pin No Symbol
45
46
47
48
49
50
51
52
53
IORQ
MREQ
RD
WR
INSTRD
RESET
NMI
BUSREQ
WAIT
Function
Input/Output
Request
Memory
Request
Read
Write
Instruction
Read Indicator
WAIT Request Input, Active Low
System Reset Schmitt Trigger Input,
Nonmaskable
Interrupt
Bus Request
Signal Direction
Bidirectional, Active
Low
Bidirectional, Active
Low
Output, Active Low
Output, Active Low
Output, Active Low
Active Low
Schmitt Trigger Input,
Active Low
Input, Active Low
Description
IORQ indicates that the CPU is accessing a
location in I/O space. RD and WR indicate
the type of access. It is an input in bus
acknowledge cycles.
MREQ Low indicates that the CPU is
accessing a location in memory. The RD,
WR, and INSTRD signals indicate the type
of access. It is an input in bus acknowledge
cycles.
RD Low indicates that the CPU is reading
from the current address location. This pin
is tristated during bus acknowledge cycles.
WR indicates that the CPU is writing to the
current address location. This pin is tristated
during bus acknowledge cycles.
INSTRD (with MREQ and RD) indicates the
CPU is fetching an instruction from memory.
This pin is tristated during bus acknowledge
cycles.
Driving the WAIT pin Low forces the CPU to
wait additional clock cycles for an external
peripheral or external memory to complete
its Read or Write operation.
This signal is used to initialize the CPU.
This input must be Low for a minimum of 3
system clock cycles, and must be held Low
until the clock is stable. This input includes
a Schmitt trigger to allow RC rise times.
The NMI input is a higher priority input than
the maskable interrupts. It is always
recognized at the end of an instruction,
regardless of the state of the interrupt
enable control bits. This input includes a
Schmitt trigger to allow RC rise times.
External devices can request the CPU to
release the memory interface bus for their
use, by driving this pin Low.
Product Specification
Architectural Overview
11