EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 191

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
ZDI Read Register Low, High, and Upper
The ZDI register Read Only address space offers Low, High, and Upper functions, which
contain the value read by a Read operation from the ZDI Read/Write Control register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the
instruction is read by a request from the ZDI Read/Write Control register. See
Table 107. ZDI Read Register Low, High and Upper(ZDI_RD_L = 10h, ZDI_RD_H =
11h, and ZDI_RD_U = 12h in the ZDI Register Read Only Address Space)
Bit
Position
4
ADL
3
MADL
2
IEF1
[1:0]
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
ZDI_RD_L,
ZDI_RD_H, or
ZDI_RD_U
Value Description
0
1
0
1
0
1
00
Value Description
00h–
FFh
R
7
0
The CPU is operating in Z80
(ADL bit = 0)
The CPU is operating in ADL MEMORY mode.
(ADL bit = 1)
The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
Reserved.
Values read from the memory location as requested by the
ZDI Read Control register during a ZDI Read operation.
The 24-bit value is supplied by {ZDI_RD_U, ZDI_RD_H,
ZDI_RD_L}.
R
6
0
R
5
0
R
4
0
®
R
3
0
MEMORY mode.
Product Specification
R
2
0
eZ80F92/eZ80F93
Zilog Debug Interface
R
1
0
Table
107.
R
0
0
184