EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 213

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
Flash Column Select Register
The column select register is a 7-bit value used to define one of the 128 bytes of Flash
memory on a single row. This register is used for all I/O Write access to Flash.
This register must be set to the proper column location within a row to program using a
single-byte Write operation. In multibyte row programming, this register is used as the
start address for the hardware incrementer.
Table 123. Flash Column Select Register; (FLASH_COL= 00FEh)
Flash Program Control Register
The Flash program control register is used to perform the functions of Mass Erase, Page
Erase, and Row Program.
Mass Erase and Page Erase are self-clearing functions. Mass Erase requires approximately
200 ms to erase the full 128 KB/64 KB of main Flash and the 256 byte Information Page.
Page Erase requires approximately 10 ms to erase a 1 KB page. Upon completion of either
a Mass Erase or Page Erase, the value of the corresponding bit is reset to 0.
While Flash is being erased, any Read or Write access of Flash memory force the CPU
into a WAIT state until the Erase operation is complete and Flash can be accessed. Reads
and Writes to areas other than Flash can proceed as usual while an Erase operation is
underway.
During row programming, any Reads of Flash memory force a WAIT condition until the
row programming operation completes or times out.
Bit
Reset
CPU Access
Note: R/W = Read/Write, R = Read Only.
Bit
Position
[7]
[6:0]
FLASH_COL
Value Description
0
00h–
7Fh
Reserved
Column address within a row of Flash memory to be used
during an I/O Write of Flash memory.
R
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
Flash Memory
R/W
0
0
206