EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 42

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Low-Power Modes
PS015313-0508
Overview
SLEEP Mode
Caution:
The eZ80F92 device provides a range of power-saving features. The highest level of
power reduction is provided by SLEEP mode. The next level of power reduction is
provided by the HALT instruction. The lowest level of power reduction is provided by the
clock peripheral power-down registers.
Execution of the CPU’s SLEEP instruction (SLP) places the eZ80F92 device into SLEEP
mode. In SLEEP mode, the operating characteristics are:
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The CPU can be brought out of SLEEP mode by any of the following operations:
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After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. See Reset on page 32 for more information.
The primary crystal oscillator is disabled
The system clock is disabled
The CPU is idle
The Program Counter (PC) stops incrementing
The 32 kHz crystal oscillator continues to operate and drive the Real-Time Clock and
the Watchdog Timer (if WDT is configured to operate from the 32 kHz oscillator)
A RESET via the external RESET pin driven Low
A RESET via a Real-Time Clock alarm
A RESET via execution of a Debug Reset command
During SLEEP mode, the CPU freezes the last address and drives the address
bus with this value. The GPIO ports remain as configured by the user. Prior to
entering SLEEP mode, the data bus is driven Low and the control signals
MREQ, CS3:0, INSTRD, BUSACK, IOREQ,RD, and WR are driven High.
Product Specification
Low-Power Modes
35