EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 50

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

PS015313-0508
GPIO Control Registers
an interrupt request signal to the CPU. Any time a port pin is configured for edge-trig-
gered interrupt, writing a 1 to that pin’s Port x Data register causes a reset of the edge-
detected interrupt. The programmer must set the bit in the Port x Data register to 1 before
entering either single or dual edge-triggered interrupt mode for that port pin.
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising
and a falling edge on the pin cause an interrupt request to be sent to the CPU.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port x Data register determines if a positive or negative edge causes an interrupt
request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges.
The 12 GPIO Control Registers operate in groups of four with a set for each Port (B, C,
and D). Each GPIO port features a Port Data register, Port Data Direction register, Port
Alternate register 1, and Port Alternate register 2.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to the
Port x Data registers, listed in
reading from the Port x Data registers always returns the current sampled value of the cor-
responding pins.
When the port pins are configured as edge-triggered interrupt sources, writing a 1 to the
corresponding bit in the Port x Data register clears the interrupt signal that is sent to the
CPU. When the port pins are configured for edge-selectable interrupts or level-sensitive
interrupts, the value written to the Port x Data register bit selects the interrupt edge or
interrupt level. See
Table 7. Port x Data Registers; (PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h)
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
Table 6
R/W
on page 39 for more information.
X
7
Table
R/W
X
7, are driven on the corresponding pins. In all modes,
6
R/W
X
5
R/W
X
4
R/W
X
3
General-Purpose Input/Output
Product Specification
R/W
X
2
eZ80F92/eZ80F93
R/W
X
1
R/W
X
0
43