EZ80F92AZ020EG Zilog, EZ80F92AZ020EG Datasheet - Page 54

• Manufacturer Part Number: EZ80F92AZ020EG
• Description: IC ACCLAIM MCU 128KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F92AZ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: EZ80F92x
• Core: eZ80
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: eZ80F920200ZCOG
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3871; EZ80F92AZ020EG

Table 12. Vectored Interrupt Operation (Continued)
PS015313-0508
Memory
Mode
Z80
ADL Mode
®
Mode 0
Nonmaskable Interrupts
ADL
Bit
1
An active Low input on the NMI pin generates an interrupt request to the CPU. This non-
maskable interrupt is always serviced by the CPU regardless of the state of the Interrupt
Enable flags (IEF1 and IEF2). The nonmaskable interrupt is prioritized higher than all
maskable interrupts. The response of the CPU to a nonmaskable interrupt is described in
detail in the eZ80
MADL
Bit
1
1
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT[7:0], bus by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
•
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
•
IEF1
IEF2
The Starting Program Counter is effectively {MBASE, PC[15:0]}
Push the 2-byte return address, PC[15:0], onto the SPL stack
Push a 00h byte onto the SPL stack to indicate an interrupt from Z80
mode (because ADL = 0)
Set the ADL mode bit to 1
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}
PC[15:0]
The ending Program Counter is {00h, PC[15:0]}
The interrupt service routine must end with RETI.L
IEF1
IEF2
The Starting Program Counter is PC[23:0]
Push the 3-byte return address, PC[23:0], onto the SPL stack
Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
(because ADL = 1)
The ADL mode bit remains set to 1
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}
PC[15:0]
The ending Program Counter is {00h, PC[15:0]}
The interrupt service routine must end with RETI.L
®
CPU User Manual (UM0077).
←
←
←
←
0
0
0
0
←
←
({00h, I[7:0], IVECT[7:0]})
({00h, I[7:0], IVECT[7:0]})
Product Specification
eZ80F92/eZ80F93
Interrupt Controller
®
47